Instruction Sets

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64 CHAPTER 2 <strong>Instruction</strong> <strong>Sets</strong>ADDADCSUBSBCRSBRSCMULMLAAddAdd with carrySubtractSubtract with carryReverse subtractReverse subtract with carryMultiplyMultiply and accumulateArithmeticANDORREORBICBit-wise andBit-wise orBit-wise exclusive-orBit clearLogicalLSLLSRASLASRRORRRXLogical shift left (zero fill)Logical shift right (zero fill)Arithmetic shift leftArithmetic shift rightRotate rightRotate right extended with CFIGURE 2.9ARM data instructions.Shift/rotateValues are transferred between registers and memory using the load-store instructionssummarized in Figure 2.12. LDRB and STRB load and store bytes rather thanwhole words,while LDRH and SDRH operate on half-words and LDRSH extends thesign bit on loading. An ARM address may be 32 bits long. The ARM load and storeinstructions do not directly refer to main memory addresses, since a 32-bit addresswould not fit into an instruction that included an opcode and operands. Instead,theARM uses register-indirect addressing. In register-indirect addressing,the value
2.2 ARM Processor 65CMPCMNTSTTEQCompareNegated compareBit-wise testBit-wise negated testFIGURE 2.10ARM comparison instructions.MOVMVNMoveMove negatedFIGURE 2.11ARM move instructions.LDRSTRLDRHSTRHLDRSHLDRBSTRBADRLoadStoreLoad half-wordStore half-wordLoad half-word signedLoad byteStore byteSet register to addressFIGURE 2.12ARM load-store instructions and pseudo-operations.stored in the register is used as the address to be fetched from memory; the resultof that fetch is the desired operand value. Thus, as illustrated in Figure 2.13, if weset r1 0 100, the instructionLDR r0,[r1]sets r0 to the value of memory location 0x100. Similarly, STR r0,[r1] would storethe contents of r0 in the memory location whose address is given in r1. There areseveral possible variations:LDR r0,[r1, – r2]
Page 2 and 3: 56 CHAPTER 2 Instruction SetsMemory
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Page 6 and 7: 60 CHAPTER 2 Instruction Sets2.2.1
Page 9: 2.2 ARM Processor 63The basic form
Page 13 and 14: 2.2 ARM Processor 67this step. Thus
Page 15 and 16: 2.2 ARM Processor 69mode fetches a
Page 17 and 18: 2.2 ARM Processor 71Example 2.4 ill
Page 19 and 20: 2.2 ARM Processor 73while (i < N) {
Page 21 and 22: 2.2 ARM Processor 75the figure show
Page 23 and 24: 2.3 TI C55x DSP 77The C55x has a nu
Page 25 and 26: 2.3 TI C55x DSP 79register mnemonic
Page 27 and 28: 2.3 TI C55x DSP 81■■S offset is
Page 29 and 30: 2.3 TI C55x DSP 83This instruction
Page 31 and 32: 2.3 TI C55x DSP 85The C55x provides
Page 33 and 34: Questions 87Q2-3 Answer the followi
Page 35 and 36: Lab Exercises 89Q2-19 Where are C55

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