Instruction Sets

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78 CHAPTER 2 <strong>Instruction</strong> <strong>Sets</strong>The block repeat start and end registers RSA0L and REA0L keep track of the startand end points of the block.The block repeat register 1 BRC1 and block repeat save register 1 BRS1 are usedto repeat blocks of instructions. There are two repeat start address registers RSA0and RSA1. Each is divided into low and high parts: RSA0L and RSA0H, for example.Four temporary registers T0,T1,T2, and T3 are used for various calculations.Two transition register TRN0 and TRN1 are used for compare-and-extractextremuminstructions. These instructions are used to implement the Viterbialgorithm.Several registers are used for addressing modes. The memory data page startaddress registers DP and DPH are used as the base address for data accesses. Similarly,the peripheral data page start address register PDP is used as a base for I/O addresses.Several registers control interrupts.The interrupt mask registers 0 and 1,namedIER0 and IER1, determine what interrupts will be recognized. The interrupt flagregisters 0 and 1, named IFR0 and IFR1, keep track of currently pending interrupts.Two other registers,DBIER0 and DBIER1,are used for debugging.Two registers,theinterrupt vector register DSP ( IVPD) and interrupt vector register host ( IVPH) areused as the base address for the interrupt vector table.The C55x registers are summarized in Figure 2.17.The C55x supports a 24-bit address space,providing 16 MB of memory as shownin Figure 2.18. Data,program,and I/O accesses are all mapped to the same physicalmemory. But these three spaces are addressed in different ways.The program spaceis byte-addressable, so an instruction reference is 24-bit long. Data space is wordaddressable,soa data address is 23 bits. (Its least-significant bit is set to 0.)The dataspace is also divided into 128 pages of 64K words each.The I/O space is 64K wordswide, so an I/O address is 16 bits. The situation is summarized in Figure 2.19.Not all implementations of the C55x may provide all 16 MB of memory on chip.The C5510,for example,provides 352 KB of on-chip memory.The remainder of thememory space is provided by separate memory chips connected to the DSP.The first 96 words of data page 0 are reserved for the memory-mapped registers.Since the program space is byte-addressable,unlike the word-addressable data space,the first 192 words of the program space are reserved for those same registers.2.3.2 Addressing ModesThe C55x has three addressing modes:■ Absolute addressing supplies an address in the instruction.■Direct addressing supplies an offset.■ Indirect addressing uses a register as a pointer.Absolute addresses may be any of three different types:■ A k16 absolute address is a 16-bit value that is combined with the DPH registerto form a 23-bit address.
2.3 TI C55x DSP 79register mnemonic descriptionAC0-AC3AR0-AR7, XAR0-XAR7BK03, BK47, BKCBRC0-BRC1BRS1accumulatorsauxiliary registers and extensions of auxiliary registerscircular buffer size registersblock repeat countersBRC1 save registerCDP, CDPH, CDPX coefficient data register: low (CDP), high (CDPH), full (CDPX)CFCTCSRDBIER0-DBIER1DP, DPH, DPXIER0-IER1IFR0-IFR1IVPD, IVPHPC, XPCPDPRETARPTCRSA0-RSA1control flow context registercomputed single repeat registerdebug interrupt enable registersdata page register: low (DP), high (DPH), full (DPX)interrupt enable registersinterrupt flag registersinterrupt vector registersprogram counter and program counter extensionperipheral data page registerreturn address registersingle repeat counterblock repeat start address registersFIGURE 2.17Registers in the TI C55x.■ A k23 absolute address is a 23-bit unsigned number that provides a full dataaddress.■ An I/O absolute address is of the form port (#1234), where the argument toport( ) is a 16-bit unsigned value that provides the address in the I/O space.Direct addresses may be any of four different types:■ DP addressing is used to access data pages. The address is calculated asA DP DPH[22 :15]|(DP D offset ). (2.2)
Page 2 and 3: 56 CHAPTER 2 Instruction SetsMemory
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Page 6 and 7: 60 CHAPTER 2 Instruction Sets2.2.1
Page 9 and 10: 2.2 ARM Processor 63The basic form
Page 11 and 12: 2.2 ARM Processor 65CMPCMNTSTTEQCom
Page 13 and 14: 2.2 ARM Processor 67this step. Thus
Page 15 and 16: 2.2 ARM Processor 69mode fetches a
Page 17 and 18: 2.2 ARM Processor 71Example 2.4 ill
Page 19 and 20: 2.2 ARM Processor 73while (i < N) {
Page 21 and 22: 2.2 ARM Processor 75the figure show
Page 23: 2.3 TI C55x DSP 77The C55x has a nu
Page 27 and 28: 2.3 TI C55x DSP 81■■S offset is
Page 29 and 30: 2.3 TI C55x DSP 83This instruction
Page 31 and 32: 2.3 TI C55x DSP 85The C55x provides
Page 33 and 34: Questions 87Q2-3 Answer the followi
Page 35 and 36: Lab Exercises 89Q2-19 Where are C55

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