Instruction Sets

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66 CHAPTER 2 Instruction SetsAddressData0 3 100r1031000 3 50 3 5r0CPUMemoryInstruction: LDR r0,[r1]FIGURE 2.13Register-indirect addressing in the ARM.0 3 201 r150 3 201SUB r1, r15, #&101Distance 5 0 3 1010 3 100 FOO0 3 5MemoryFIGURE 2.14Computing an absolute address using the PC.loads r0 from the address given by r1 r2, whileLDR r0,[r1, #4]loads r0 from the address r1 4.This begs the question of how we get an address into a register—we need to beable to set a register to an arbitrary 32-bit value. In the ARM,the standard way to seta register to an address is by performing arithmetic on the program counter, whichis stored in r15. By adding or subtracting to the PC a constant equal to the distancebetween the current instruction (i.e.,the instruction that is computing the address)and the desired location,we can generate the desired address without performing aload. The ARM programming system provides an ADR pseudo-operation to simplify
2.2 ARM Processor 67this step. Thus, as shown in Figure 2.14, if we give location 0x100 the name FOO,we can use the pseudo-operationADR r1,FOOto perform the same function of loading r1 with the address 0x100.Example 2.2 illustrates how to implement C assignments in ARM instruction.Example 2.2C assignments in ARM instructionsWe will use the assignments of Figure 2.7. The semicolon (;) begins a comment after aninstruction, which continues to the end of that line. The statementx (a b) c;can be implemented by using r0 for a, r1forb, r2forc, and r3 for x. We also need registersfor indirect addressing. In this case, we will reuse the same indirect addressing register, r4,for each variable load. The code must load the values of a, b, and c into these registers beforeperforming the arithmetic, and it must store the value of x back to memory when it is done.This code performs the following necessary steps:ADR r4,a ; get address for aLDR r0,[r4] ; get value of aADR r4,b ; get address for b, reusing r4LDR r1,[r4] ; load value of bADD r3,r0,r1 ; set intermediate result for x to a + bADR r4,c ; get address for cLDR r2,[r4] ; get value of cSUB r3,r3,r2 ; complete computation of xADR r4,x ; get address for xSTR r3,[r4] ; store x at proper locationThe operationy a ∗ (b c);can be coded similarly, but in this case we will reuse more registers by using r0 for both a andb,r1forc, and r2 for y . Once again, we will use r4 to store addresses for indirect addressing.The resulting code isADR r4,b ; get address for bLDR r0,[r4] ; get value of bADR r4,c ; get address for cLDR r1,[r4] ; get value of cADD r2,r0,r1 ; compute partial result of yADR r4,a ; get address for a
Page 2 and 3: 56 CHAPTER 2 Instruction SetsMemory
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Page 6 and 7: 60 CHAPTER 2 Instruction Sets2.2.1
Page 9 and 10: 2.2 ARM Processor 63The basic form
Page 11: 2.2 ARM Processor 65CMPCMNTSTTEQCom
Page 15 and 16: 2.2 ARM Processor 69mode fetches a
Page 17 and 18: 2.2 ARM Processor 71Example 2.4 ill
Page 19 and 20: 2.2 ARM Processor 73while (i < N) {
Page 21 and 22: 2.2 ARM Processor 75the figure show
Page 23 and 24: 2.3 TI C55x DSP 77The C55x has a nu
Page 25 and 26: 2.3 TI C55x DSP 79register mnemonic
Page 27 and 28: 2.3 TI C55x DSP 81■■S offset is
Page 29 and 30: 2.3 TI C55x DSP 83This instruction
Page 31 and 32: 2.3 TI C55x DSP 85The C55x provides
Page 33 and 34: Questions 87Q2-3 Answer the followi
Page 35 and 36: Lab Exercises 89Q2-19 Where are C55

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