Instruction Sets

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68 CHAPTER 2 <strong>Instruction</strong> <strong>Sets</strong>LDR r0,[r4] ; get value of aMUL r2,r2,r0 ; compute final value of yADR r4,y ; get address for ySTR r2,[r4] ; store value of y at proper locationThe C statementz (a 2) | (b & 15);can be coded using r0 for a and z, r1forb, and r4 for addresses as follows:ADR r4,aLDR r0,[r4]MOV r0,r0,LSL 2ADR r4,bLDR r1,[r4]AND r1,r1,#15ORR r1,r0,r1ADR r4,zSTR r1,[r4]; get address for a; get value of a; perform shift; get address for b; get value of b; perform logical AND; compute final value of z; get address for z; store value of zWe have already seen three addressing modes: register, immediate, and indirect.The ARM also supports several forms of base-plus-offset addressing, which isrelated to indirect addressing. But rather than using a register value directly asan address, the register value is added to another value to form the address. Forinstance,LDR r0,[r1,#16]loads r0 with the value stored at location r1 16. Here,r1 is referred to as the baseand the immediate value the offset. When the offset is an immediate, it may haveany value up to 4,096;another register may also be used as the offset.This addressingmode has two other variations:auto-indexing and post-indexing. Auto-indexingupdates the base register, such thatLDR r0,[r1,#16]!first adds 16 to the value of r1, and then uses that new value as the address. The! operator causes the base register to be updated with the computed address sothat it can be used again later. Our examples of base-plus-offset and auto-indexinginstructions will fetch from the same memory location, but auto-indexing will alsomodify the value of the base register r1. Post-indexing does not perform the offsetcalculation until after the fetch has been performed. Consequently,LDR r0,[r1],#16will load r0 with the value stored at the memory location whose address is given byr1, and then add 16 to r1 and set r1 to the new value. In this case, the post-indexed
2.2 ARM Processor 69mode fetches a different value than the other two examples, but ends up with thesame final value for r1 as does auto-indexing.We have used the ADR pseudo-op to load addresses into registers to access variablesbecause this leads to simple, easy-to-read code (at least by assembly languagestandards). Compilers tend to use other techniques to generate addresses, becausethey must deal with global variables and automatic variables.2.2.3 Flow of ControlThe B (branch) instruction is the basic mechanism in ARM for changing the flow ofcontrol.The address that is the destination of the branch is often called the branchtarget. Branches are PC-relative—the branch specifies the offset from the currentPC value to the branch target. The offset is in words, but because the ARM is byteaddressable,the offset is multiplied by four (shifted left two bits, actually) to form abyte address. Thus, the instructionB #100will add 400 to the current PC value.We often wish to branch conditionally,based on the result of a given computation.The if statement is a common example. The ARM allows any instruction, includingbranches, to be executed conditionally. This allows branches to be conditional, aswell as data operations. Figure 2.15 summarizes the condition codes.EQ Equals zero Z 5 1NE Not equal to zero Z 5 0CS Carry set C 5 1CC Carry clear C 5 0MI Minus N 5 1PL Nonnegative (plus) N 5 0VS Overflow V 51VC No overflow V 5 0HI Unsigned higher C 5 1 and Z 5 0LS Unsigned lower or same C 5 0 or Z 5 1GE Signed greater than or equal N 5 VLT Signed less than N VGT Signed greater than Z 5 0 and N 5 VLE Signed less than or equal Z 5 1 or N VFIGURE 2.15Condition codes in ARM.
Page 2 and 3: 56 CHAPTER 2 Instruction SetsMemory
Page 4 and 5: 58 CHAPTER 2 Instruction Setschange
Page 6 and 7: 60 CHAPTER 2 Instruction Sets2.2.1
Page 9 and 10: 2.2 ARM Processor 63The basic form
Page 11 and 12: 2.2 ARM Processor 65CMPCMNTSTTEQCom
Page 13: 2.2 ARM Processor 67this step. Thus
Page 17 and 18: 2.2 ARM Processor 71Example 2.4 ill
Page 19 and 20: 2.2 ARM Processor 73while (i < N) {
Page 21 and 22: 2.2 ARM Processor 75the figure show
Page 23 and 24: 2.3 TI C55x DSP 77The C55x has a nu
Page 25 and 26: 2.3 TI C55x DSP 79register mnemonic
Page 27 and 28: 2.3 TI C55x DSP 81■■S offset is
Page 29 and 30: 2.3 TI C55x DSP 83This instruction
Page 31 and 32: 2.3 TI C55x DSP 85The C55x provides
Page 33 and 34: Questions 87Q2-3 Answer the followi
Page 35 and 36: Lab Exercises 89Q2-19 Where are C55

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