Nonvolatile, I2C-Compatible 64-Position, Digital Potentiometer ...

AD5258I 2 C INTERFACENote that the wiper’s default value, prior to programming theEEPROM, is midscale.1. The master initiates data transfer by establishing a STARTcondition when a high-to-low transition on the SDA lineoccurs while SCL is high (see Figure 4). The next byte isthe slave address byte, which consists of the slave address(first 7 bits) followed by an R/W bit (see Table 6). When theR/W bit is high, the master reads from the slave device.When the R/W bit is low, the master writes to the slavedevice.The slave address of the part is determined by two threestate-configurableAddress Pins AD0 and AD1. The state ofthese two pins is registered upon power-up and decodedinto a corresponding I 2 C 7-bit address (see Table 5). Theslave address corresponding to the transmitted address bitsresponds by pulling the SDA line low during the ninthclock pulse (this is termed the slave acknowledge bit).At this stage, all other devices on the bus remain idle whilethe selected device waits for data to be written to, or readfrom, its serial register.2. Writing: In the write mode, the last bit (R/W) of the slaveaddress byte is logic low. The second byte is the instructionbyte. The first three bits of the instruction byte are thecommand bits (see Table 6). The user must choose whetherto write to the RDAC register, EEPROM register, oractivate the software write protect (see Table 7 to Table 10).The final five bits are all zeros (see Table 13 to Table 14).The slave again responds by pulling the SDA line low duringthe ninth clock pulse.The final byte is the data byte MSB first. Don’t cares can beleft either high or low. In the case of the write protectmode, data is not stored; rather, a logic high in the LSBenables write protect. Likewise, a logic low will disablewrite protect. The slave again responds by pulling the SDAline low during the ninth clock pulse.3. Storing/Restoring: In this mode, only the address andinstruction bytes are necessary. The last bit (R/W) of theaddress byte is logic low. The first three bits of theinstruction byte are the command bits (see Table 6). Thetwo choices are transfer data from RDAC to EEPROM(store), or from EEPROM to RDAC (restore). The final fivebits are all zeros (see Table 13 to Table 14).4. Reading: Assuming the register of interest was not justwritten to, it is necessary to write a dummy address andinstruction byte. The instruction byte will vary dependingon whether the data that is wanted is the RDAC register,EEPROM register, or tolerance register (see Table 11 toTable 16).After the dummy address and instruction bytes are sent, arepeat start is necessary. After the repeat start, anotheraddress byte is needed, except this time the R/W bit is logichigh. Following this address byte is the readback bytecontaining the information requested in the instructionbyte. Read bits appear on the negative edges of the clock.Don’t cares may either be in a high or low state.The tolerance register can be read back individually (seeTable 15) or consecutively (see Table 16). Refer to the ReadModes section for detailed information on the interpretationof the tolerance bytes.5. After all data bits have been read or written, a STOPcondition is established by the master. A STOP condition isdefined as a low-to-high transition on the SDA line whileSCL is high. In write mode, the master pulls the SDA linehigh during the tenth clock pulse to establish a STOPcondition (see Figure 45). In read mode, the master issues ano acknowledge for the ninth clock pulse (that is, the SDAline remains high). The master then brings the SDA linelow before the tenth clock pulse, and then raises SDA highto establish a STOP condition (see Figure 46).A repeated write function gives the user flexibility toupdate the RDAC output a number of times afteraddressing and instructing the part only once. Forexample, after the RDAC has acknowledged its slaveaddress and instruction bytes in the write mode, the RDACoutput is updated on each successive byte until a STOPcondition is received. If different instructions are needed,the write/read mode has to start again with a new slaveaddress, instruction, and data byte. Similarly, a repeatedread function of the RDAC is also allowed.Rev. 0 | Page 15 of 24