Test During Burn-in Evolution - BiTS Workshop

Burn-in & TestSocket WorkshopWELCOMEMarch 2 - 5, 2003Hilton Phoenix East / Mesa HotelMesa, ArizonaSponsored By The IEEE Computer SocietyTest Technology Technical Counciltttc

Burn-in & Test SocketWorkshopSession 1Monday 3/03/03 8:30AMTechnical ProgramTest And Burn-in Operations“Full Wafer Contact Burn-In And Test - The Ultimate In Parallelism”Steve Steps - AEHR Test Systems“Strategic Use Of Burn In”Tamas Kerekes - NplusT Semiconductor Application Center S.r.l.“A Flexible Electrical Interface Design For The Fixture BetweenTester And DUT To Achieve Reduced Cost And Leadtime In ATEToolings”Koh Tuan Meng - Micron Semiconductor AsiaLim Kok Lay - Micron Semiconductor Asia(Presented by: Steve Hamren - Micron Semiconductor)

Full Wafer ContactBurn-In and Test– The Ultimate inParallelism?2003 Burn-in and Test Socket WorkshopMarch 2 - 5, 2003Steve StepsAehr Test Systems

Agenda• Test During Burn-in Evolution• Burn-in Process Evolution• Test Evolution• Convergence Point• ConclusionsBiTS 2003 Steps 2

Test During Burn-in Evolution• Bake• Static Burn-in (Power only)• Dynamic Burn-in (Plus input)• Output Monitoring Burn-in (Check someoutputs)• Burn-in and Test (Full functional test)All performed highly parallelBiTS 2003 Steps 3

Parallel Testing128 Tester I/O Channels X 32 CS = 4096 Total Device I/O Pins161616161616161612345678CS1……………………249250251252253254255256CS32BiTS 2003 Steps 4

Value of Offloading Final Test• If the burn-in system can perform a giventest, it can be much cheaper• Opportunity to perform tests at the sametime as burn-in• Experience has shown as much as 80% offinal test time can be performed duringburn-inBiTS 2003 Steps 5

Traditional Test ProcessPre Burn-in Test- DC ParametricsTest- Gross FunctionalTestMonitored Burn-in- Dynamic Stressing- Long Functional TestFinal Test- DC Parametrics Test- AC Parametrics Test- Speed Sort- Pattern Sensitivity Tests- Long Cycle Time Tests- Data Retention Tests- Refresh TestsBiTS 2003 Steps 6

Parallel Test During Burn-inPre Burn-in Test- DC ParametricsTest- Gross FunctionalTestMassively Parallel Test- Dynamic Stressing- Long Functional Test- Pattern Sensitivity Tests- Long Cycle Time Tests- Data Retention Tests- Refresh TestsFinal Test- DC Parametrics Test- AC Parametrics Test- Speed SortTest OffloadBiTS 2003 Steps 7

Burn-in Process Evolution• Assembly/System• Packaged part• Bare die• Full WaferBiTS 2003 Steps 8

Wafer-Level Burn-In and Test• Full WaferContact• Full functionaltest capability• Thermal StressChamberBiTS 2003 Steps 9

Progression To Wafer-Level• Reduce repair cost of burn-in fallout– More critical if assembly non-repairable– Reduce excessive burn-in• Reduce wasted packaging/assembly• Faster feedback to front-end• KGD for SIP, MCM, etc. requires either bare dieor wafer-level burn-inBiTS 2003 Steps 10

Test Evolution – External Test• Full I/O speed– Cost per channel very high ($Ks/channel)– Signal cable must be very short– GHz testing very difficult• Full I/O width– One channel per device pin– Total device count per test very limitedBiTS 2003 Steps 11

Test Evolution – Structural Test• Typically scan chain based• External data clock speed requirements vastlyreduced• On chip ATPG– I/O width significantly reduced (compressed)– Still can have edge timing constraints• Logic BIST– Device pin I/O speed

Wafer-Level Burn-in with BIST• Logical convergence of:– Test During Burn-in Evolution (Full functional)– Burn-in Process Evolution (Wafer-level)– Test Evolution (Logic BIST)• Key enablingtechnologies:– Full wafer contact– Massively parallel testing– Logic BISTBiTS 2003 Steps 13

Wafer-Level Logic Test, no BISTUsing 4 site tester:LoadWaferTestStep. . . .Test Step Test TestFor 300 die wafer, about 80 Test cyclesBiTS 2003 Steps 14

Wafer-Level Logic Test, BISTLoadAlignTestPollOutputOnly one test cycle required20-40x TimeReduction!BiTS 2003 Steps 15

Conclusion• Wafer-Level burn-in and test using BIST isnext step in evolution for test during burn-in• Higher percentage of test can be performedduring burn-in and thus offloaded from highspeed final testBiTS 2003 Steps 16

Strategic Use of Burn In2003 Burn-in and Test Socket WorkshopMarch 2 - 5, 2003Tamas KerekesELES Semiconductor Equipment

Agenda Pressure on the Burn-In Possibility of Adding Values Technical Solutions for Doing this Case Studies3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 2

Pressure on the Burn-In

Market TrendsTime-to-marketNo matureprocessesTime-to-yieldOutsourcingLow marginsContinuousneed ofprocess andproductqualificationCost controlProcesscontrol3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 4

Technology Trends‣ Low geometry‣ High transistor count‣ Integration, system-on-chip, analogbehavior‣ New packages‣ High frequency‣ Low voltage, high power‣ Non-deterministic timing‣ High IO count‣ Critical reliability‣ Expensive sockets‣ Multi-layer, fine-pitch boards‣ Thermal control‣ High performance electronics‣ Need of qualified engineering3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 5

Keeping pace with theMoore lawrequires huge R&D andengineering… and …it costs !3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 6

Dilemmacostvalue?1 + 1 + 1 = 1ScreeningPerformanceEngineeringQuality3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 7

Costs and complexity are strictlyrelated to the elementary functionof the burn-in:detecting weakness ofproducts and processes…… thus there is no easy way toreduce or avoid these expenses3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 8

Increasing the Value of Burn-In

New Equationcostvalue1 + 1 + 1 = 3?Screening +PerformanceEngineeringQuality3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 10

Possible Added Values Yield increase Test time saving Efficient management of the burn-in area3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 11

The Equation Againcostvalue1 + 1 + 1 = 3PerformanceEngineeringScreening +Increased yield +Test cost saving +Efficient operationQuality3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 12

Yield Increase During ramp-up (time-to-yield) During manufacturing cycle (process control) Requires:‣ Detailed on-line reliability data generation‣ Real-time data processing‣ Automated feedback of the data3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 13

Test Cost Saving• Manufacturing - Goals– Reduced test-time on ATE– Better quality control in the production cycle• Operations– TDBI (full burn-in)– Batch Testing (when no burn-in is required)• Qualification– Replacement of the intermittent test on ATE withcontinuous in-line testing• Not only for memories3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 14

Area Management Statistical Process Control‣ Utilization tracking‣ Maintenance tracking‣ Defect analysis Area Control‣ Lot tracking‣ Scheduling‣ Integration Expert System‣ “tell the operator what to do”3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 15

Technical Solutions

Key Factors Equipment Data management Organization and methodologies3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 17

Equipment Full use of DFT methodologies,for increased visibility‣ Scan, JTAG, SoftBIST, … Coverage of a wide range of devices(in the same chip)‣ Analog, digital, memory Flexible, programmable test flow‣ Functional tests‣ Characterizations (smoo, bitmap, …) Flexible, programmable data generation3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 18

Flexible Device ManagementuCPSPOWERSUPPLIESFPGAIOIOCHANNELSMEMDevice specific algorithms (not only flat vectors) runon the tester electronics and on the device under test3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 19

Example: Bitmap3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 20

Example: Distribution400.000350.000300.000250.000200.000150.000100.000S1S2S3S450.000-Vt3.0503.1503.2503.3503.4503.5503.6503.7503.8503.9504.0504.1504.2503/19/2003 Strategic Use of Burn In (Tamas Kerekes) 21

Data Collection SystemTDBI1TDBI2TDBInLOCALCONTROLKNOWLEDGEDATABASE Support‣ Shared recipe data base‣ Remote monitor‣ BLU integration‣ Diagnostic toolsCOMPANY NETWORKOF WEB ACCESS Analysis‣ Summary reporting‣ Correlation withknowledge data base‣ Characterizationtools for failure analysis Expert system‣ Utilization data‣ Maintenance data‣ Diagnostics data‣ Fail concentration3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 22

Development ToolsSPECIFICATIONSAPPLICATIONDEVICESPECSTESTVECTORSETDEVICECHARACTERIZATIONDATADEVELOPMENTPROCESSBOARDDESIGNTESTPROGRAM Vector translation and IO assignment (simple case) Device specific algorithms (C) and test flow description(scripting) GUI for automated script generation3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 23

ART 200 Flexible hardware andsoftware structure High electricalperformance Standard and user specificalgorithms Scripting language for testflow Data collection andprocessing tools Area management support3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 24

TeamworkDesignerProcess EngineerTest EngineerReliabilityApplication SupplierEquipment SupplierCommon EffortDeviceTest FlowEquipmentApplicationCommon Result3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 25

Case Studies

Case Study 1:High Coverage QualificationStandard69%100ATE% of die coveredstress factordata generation“Strategic”92%141BI + ATE55 dayscycle time45 days3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 27

Case Study 2:New Embedded NVM Process Same tools used for characterization,qualification and production quality control Yield ramp-up from 7% to 95% in 1 WKusing characterization data generated inproduction3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 28

Case Study 3:TDBI on Embedded NVM Embedded NVM tested only during burn-in Test result correlation proven Fully integrated burn-in area ATE test time and ATE investment reducedby 60% (6 M$) Total process cost reduced by 40%3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 29

Case Study 4:Fully Parallel Test on Flash 64 Mbit TSOP56 All functional test steps implemented in aparallel test (“burn-in like”) environment, asan additional process step ATE runs only DC and AC tests (85% testtime saving) Total process cost reduced by 50% Increased outgoing reliability (cycling“gratis”), value not measured yet3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 30

thank youfor your time andconsideration3/19/2003 Strategic Use of Burn In (Tamas Kerekes) 31

A FLEXIBLE ELECTRICAL INTERFACEDESIGN FOR THE FIXTURE BETWEENTESTER AND DUT TO ACHIEVEREDUCED COST AND LEADTIMEIN ATE TOOLINGS2003 Burn-in and Test Socket WorkshopMarch 2 - 5, 2003Koh Tuan MengLim Kok Lay

Agenda• Background• Objectives• Design Concept (Flexi-Interface)• Prototype Evaluations Data• Conclusions

Background• Device Specific Electrical Inteface– Tester channels routed to DUT (device under test)according to device pinouts.– No flexibility in toolings.• High Toolings Cost– Existing toolings cannot be used if device pinoutsare different.• Long Leadtime For Toolings– Tpyical cycle time for building a new electricalinterface is about 2 to 3 months.

Objectives• To have better toolings flexibility• Reduce Test toolings cost.• Reduce Test toolings leadtime.

Design Concept (Flexi-Interface)Conventional TestInterface FixtureFlexi-Interface TestInterface FixtureSocketSocketBoardSocketAdaptor BoardInterconnectSocket BoardChangeoverkits(DeviceSpecific)DeviceSpecificUniversalBaseAssembly

Interconnect MaterialShin-Etsu Interconnector (SMM)Courtesy of SHIN-ETSU (http://www.shinpoly.com)

Prototype Evaluations DataTime-Domain MeasurementsTDR (Time Domain Reflectometry)measurements were taken tocapture any abnormalities on theimpedance profiles for thecomplete signal path.The impedance dips below50ohms at the portion of the SMMinterconnect. The SMMinterconnect is not impedancecontrol and hence causes someimpedance mismatch (it has acapacitive effect).

Prototype Evaluations DataTime-Domain Measurements73.999ps215.20ps132.50psAdaptor Board – PD5TDT (Time Domain Transmission)measurements were taken on thebare boards to derive the actualpropagation delay introduced bythe SMM interconnect.The delay is only about 9ps.

1981Prototype Evaluations DataFrequency-Domain MeasurementsUniversal BoardFreque ncy (MHz)50108.5167225.5284342.5401459.5518576.5635693.5752810.5869927.59861045110311621220127913371396145415131571163016881747180518641922S21 (dB)-5.8 -4.8 -3.8 -2.8 -1.8 -0.8 0.2Insertion Loss measurements were taken on thebare boards to check for the signal degradationcaused by the SMM interconnect.P19-18P45-44

Prototype Evaluations DataFrequency-Domain MeasurementsAdaptor Board5010916722628434340146051857763569475281186992898610451103116212201279133713961454151315711630168817471805186419221981Frequency (MHz)0.2-1. 8-3. 8-5. 8-7. 8-9. 8P19-18P45-44S21 (dB)-11.8-13.8-15.8Adaptor Board

Prototype Evaluations DataFrequency-Domain MeasurementsSMMFrequency (MHz)0-2-4-6-8-10S21 (dB)5010916722628434340146051857763569475281186992898610451103116212201279133713961454151315711630168817471805186419221981P45-44P19-18-12-14The frequency bandwidth for the complete assemblydrops to 700MHz (@ 1dB insertion loss).

Prototype Evaluations DataA short program was developed on the ATE tester tocheck for the rise time, cross-talk, overshoot andundershoot performance of the flexible electricalinterface.w/o interconnect :840pswith interonnect :958psw/o interconnect :914pswith interonnect :1.14nsRisetimeFalltimeWith the interconnect, the risetime is degraded byabout 100ps.

Prototype Evaluations DataCrosstalk MeasurementsUniversalUniversalAdaptor Board (SMM)Adaptor Board (SMM)Board TypeOvershoot / UndershootBoard TypeOvershoot / UndershootUniversal Board125mv / 40mvUniversal Board80mv / 65mvAdaptor Board(SMM)292mv / 60mvAdaptor Board(SMM)317mv / 85mvThe interconnect causes about 10% overshoot voltage.

Conclusions• With the data collected in both the Time &Frequency domains, the flexible electricalinterface concept has been proven to beviable for device testing (for SDRAM). Thereis, however, still room for improvements onthe interface between board to board.• The next challenge would be to prove out theFlexi-interface concept for higher speeddevice testings (DDR II & beyond).