Burn-in & Test Socket Workshop - BiTS Workshop

Burn-in & TestSocket WorkshopMarch 2 - 5, 2003Hilton Phoenix East / Mesa HotelMesa, ArizonaSponsored By The IEEE Computer SocietyTest Technology Technical Counciltttc

COPYRIGHT NOTICE• The papers in this publication comprise the proceedings of the 2003BiTS Workshop. They reflect the authors’ opinions and are reproduced aspresented , without change. Their inclusion in this publication does notconstitute an endorsement by the BiTS Workshop, the sponsors, or theInstitute of Electrical and Electronic Engineers, Inc.· There is NO copyright protection claimed by this publication. However,each presentation is the work of the authors and their respectivecompanies: as such, proper acknowledgement should be made to theappropriate source. Any questions regarding the use of any materialspresented should be directed to the author/s or their companies.

Burn-in & Test SocketWorkshopTechnical ProgramSession 3Tuesday 3/04/03 8:00AMSocket And Board Development“CAF Effect: Challenges For Fine Pitch Burn-in Board Design”K. W. Low - Intel CorporationAnthony Yeh Chiing Wong - Intel CorporationHon Lee Kon - Intel Corporation“Automated Burn-in Socket Testing And Evaluation”Holger Hoppe - Infineon Technologies AG“Thermal Testing Of Burn-In Sockets”James Forster - Texas InstrumentsSavithri Subramanyam - Texas Instruments

CAF Effect:Challenges for Fine Pitch BIB DesignAnthony Wong Yeh ChiingKon Hon LeeLow KWIntel Corporation

•OverviewAgenda• Background & Definition• CAF Formation• Factors Contributing to CAF• Fine Pitch BIB Design Rules• Best Known Test Methods & Issues.• Findings on PCB Materials Investigated• Technical Challenges.Anthony WongHL Kon/Low KWBiTS 2003 2

Overview• Most Wireless & Networking products have continuouslyshrunk in size due to consumer need for smaller, lighter,powerful, and portable devices.• Over the years, technology companies have migrated theproduct pin pitch from 1.27mm to 0.5mm and less.1.27mm pitch0.5mm pitch• Due to the tight pitch, fine pitch PCBs are moresusceptible to CAF failure which will cause the board tofail electrically in the field after some time in use.Anthony WongHL Kon/Low KWBiTS 2003 3

Background & Definition• CAF is the acronym for Conductive Anodic Filament.• Discovered by Bell Lab in 1976.• Further research has been performed by U of Maryland(CALCE), Georgia Institute of Technology & SunMicrosystems.• CAF is the growth of a coppercontainingfilament subsurfacealong the epoxy-glass interface,from anode to cathode.Anthony WongHL Kon/Low KWSource:School of Materials Science & Engineering,GIT, Atlanta, GABiTS 2003 4

CAF Formation• Glass/epoxy bonds degrade – due to mechanical stress,poor quality coupling agent, etc.• In a humid environment, water absorption occurs and createsan aqueous medium that provides an electrochemicalpathway that facilitates the transport of corrosion products.• Water acts as the electrolyte, copper circuitry as anode &cathode and operating voltage as driving potential.• H+ (pH lower) and OH- (pH higher) creates a pH gradient.• Copper is passivated in region of pH 7 to 11 but becomescorrosive at pH below 7 and potentials greater than 0.2V.• The anodic copper ions travel along the epoxy/fiber interfaceattracted to the cathode.Anthony WongHL Kon/Low KWBiTS 2003 5

Factors Contributing to CAF(1)• Material:• Several experiments have been done by PCB laminatesuppliers.• Most PCB Materials are only CAF ResistiveAnthony WongHL Kon/Low KWBiTS 2003 6

Factors Contributing to CAF(2)• Conductor Configuration:Most susceptibleSource:School of Materials Science & Engineering, GIT, Atlanta, GALeast susceptible• Voltage Gradient Effects: 3-8V/mils• Solder Flux/HASL(Hot Air Solder Leveling) FluidComposition:• Testing shows that polyglycols diffuse into epoxy duringsoldering and increases moisture absorption by thesubstrate.• Thermal Excursions:• Temperature , amount of polyglycol absorption• Will weaken the bonding between epoxy and glass fibersdue to difference in Coefficient of Thermal Expansion.Anthony WongHL Kon/Low KWBiTS 2003 7

Factors Contributing to CAF(3)• Cleaning:• Polyglycol residues from soldering process.• PCB Storage & Use: Ambient Humidity Effects.• Humidity threshold depends upon operating voltage andtemperature.• Moisture absorption can occur during any part of the PCB’slifetime.• PCB exposure to high humidity conditions duringtransportation and storage can be problematic.Anthony WongHL Kon/Low KWBiTS 2003 8

Fine Pitch BIB Design RulesProduct PinPitch1.27mm1.00mm0.80mm0.65mm0.50mm0.50mm0.40mmFine Pitch PCB design distancesX-Pitch(mils)5039.431.525.619.719.715.7XYZ – Holesize (mils)332515.7510.2686Z-Via orPin hole sizeY – edge to edgedistance (mils)1714.415.7515.413.711.79.7Reduction inedge to edgedistance• Y is a critical dimension; closer it is, more susceptible to CAF• Hole/Via determined by drill bit size and positional accuracy.Anthony WongHL Kon/Low KWBiTS 2003 9

Best Known Test Methods & Issues(1)• Two primary test methods for CAF testing:• Surface Insulation Resistance (SIR) Test methodintroduced by Telcordia.– GR-78-CORE (IPC-TM-650, Section 2.6.14.1)– Test for surface electro migration and for characterizingPCB laminates, soldering fluxes, solder masks &conformal coating.– Test valid for a 25 year desired minimum product life.Anthony WongHL Kon/Low KWBiTS 2003 10

Best Known Test Methods & Issues(2)• CAF Test method– Sun Microsystems’ CAF Pattern (IPC in review)– Use to evaluate Alternate materials, design and PCBmanufacturing processes.– Valid for a 20 year desired minimum product life.– Four test patterns available to cover the four criticalPCB designs.• In Line Test Pattern ATestPatternA1A2A3Pad size34 mils32 mils30 milsDrill hole size29.2 mils25 mils20 milsVia edge to edgedistance10.8 mils15.0 mils20.0 milsA427 mils14.5 mils25.5 milsAnthony WongHL Kon/Low KWBiTS 2003 11

Best Known Test Methods & Issues(3)• Staggered Test Pattern BTestPatternPad sizeDrill hole sizeVia edge to edgedistanceB137 mils32 mils10.4 milsB235 mils28 mils14.4 milsB333 mils22.5 mils19.9 milsB430 mils• Via to Plane Test Pattern C18 mils24.4 milsTestPatternPad sizeDrill hole sizeVia edge to antipadedgeC125 mils14.5 mils5.25 milsC228 mils14.5 mils6.75 milsC333 mils14.5 mils9.25 milsC438 mils14.5 mils11.75 mils• Trace to Trace Test Pattern DAnthony WongHL Kon/Low KWBiTS 2003 12

Best Known Test Methods & Issues(4)• Sun Microsystems test pattern are used to test:• Process• Drilled hole roughness• Hole clean process• Drilled hole to inner layer registration• Material• Reinforcement type• Adhesion treatment used on electrical glass• Resin type• Copper tooth profile• PCB design• Layer to layer dielectric thickness• Via edge to via edge spacing• Via location (In or out of line with the reinforcement weave direction)• Via edge to antipad clearance• Hole size and board thickness – drill wander• Environmental• Temperature• Humidity• Voltage BiasAnthony WongHL Kon/Low KWBiTS 2003 13

Best Known Test Methods & Issues(5)• SIR test is only valid for surface test.• Sun’s CAF testing setup does not represent today’s finepitch Burn-in board environment.• Does not comprehend the current expectation of 1-3 yearsusage.• Slightly variation in the PCB via edge to edge design.Product Pin PitchPowerTemperatureHumilityProduct lifeDesign –via edge to edgeSun CAF test10V & 100V85C65%20 years10.4 – 25.5 milsTypical BIRequirements1.3-4.6V65-125C40-85%1-3 years9.7 – 17 milsAnthony WongHL Kon/Low KWBiTS 2003 14

Findings on PCB Materials Investigated• Evaluation done on one material showed that no surfaceelectro migration occurred and it is CAF resistive.• Others investigated include non-woven Aramid enforcedmaterial.LaminateLaminateVoidsVoidsAnthony WongHL Kon/Low KWBiTS 2003 15

Technical Challenges• CAF test standardization• An approved industry standard.• Better CAF test data interpretation method.• Must be able to validate CAF free for product lifetimedurations (1-3 years).• New CAF free PCB material• Need to develop a CAF free PCB material for the future.• Should not have any side effect such as high CTE or highwater absorption.• New Manufacturing process• Stability of process and consistent PCB yield.• CAF test data sharing and collaboration.• PCB material - BT Resin, Polyimide, FR4, Thermount etc.• Lack of conclusive data from Laminate suppliers.• Accredited forum for technical consultation.Anthony WongHL Kon/Low KWBiTS 2003 16

BiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003Automated Burn-in SocketTesting and EvaluationHolger HoppeInfineon Technologies AGholger.hoppe@infineon.comHolger HoppePage 1 .

A g e n d aBiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003‣ Requirements for Burn-in sockets‣ Release of Burn-in sockets‣ Burn-in process simulation‣ ConclusionsHolger HoppePage 2 .

IntroductionBiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003‣ Burn-in sockets: more complicated than obvious in order to havea stable and reliable burn-in process‣ Burn-in sockets in memory mass production: very cost intensive‣ Life time expectation: > 2 yearsrespectively > 600 burn-in cycles‣ Burn-in cycle: loading (opening socket, contacting, closing socket) temperature cycling (room temp high temp room temp) unloading (opening, unloading, closing).‣ Better to know burn-in socket performance before big volumeorders than after 1 year production experience.Holger HoppePage 3 .

Requirements for burn-in socketsBiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003‣Electrical demandGood (low and stable resistance) and reliable contact of theDUT (device under test) to the test and burn-in equipmentfor proper electrical function and ageing process in the burninsystems‣Mechanical demandStability (springs, contact force) for long term useGood device guidance during load (drop off) for massproductionHolger HoppePage 4 .

Evaluation and release of burn-in socketsBiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003‣ObjectiveEvaluate electrical and mechanical performance of new burn-insockets in the labApproaching real burn-in conditions: to simulate all processesdone with burn-in sockets in real production in short timeThermal stress with electrical function: Burn-in simulationMechanical stress + tests : Loader/Unloader simulationAlso possible: Ageing evaluation of used burn-in sockets aftera few hundreds runs in production (in comparison with anunused socket of same type)Holger HoppePage 5 .

Fully Automated Burn-In Socket Tester (FABIST) I‣General featuresBiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003 Fully automated system running LabView software(mechanical control, heating control, measurement control) Loader / Unloader function with industrial robot Heating / Cooling ramp freely programmable Device exchange after each cycle, freely programmable Simultaneously 4 (different) sockets testable Engineering field for further investigations andLoader/Unloader simulation Highly flexible systemHolger HoppePage 6 .

Fully Automated Burn-In Socket Tester IIBiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003‣General features (cont.) 5 axis robot (Mitsubishi) for automatic cycles (load / unload/ open+close chamber / engineering), accuracy 0.02mm 2 x 6 Jedec trays or waffle pack for >= 1200 device (300cycles) Universal presizer Max. socket size 50x50mm Temperature range: RT - 150°C (+/- 1°) Temperature ramp: >=10 K / min (up / down) freelyprogrammable = approx. 7 days for 300 cylces NI - Industrial controller (PC-based) Keithley 22 bit Multimeter with 4 x 32 channelsHolger HoppePage 7 .

Fully Automated Burn-In Socket Tester IIIBiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003Overview I5-axis-robotHolger HoppePage 8 .

Fully Automated Burn-In Socket Tester IVBiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003Overview IIHolger HoppePage 9 .Temperature Chamber

Burn-in Simulation IBiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003‣ Minimum 300 Burn-in cycles (approx. 1 year use)‣ Load DeviceHolger HoppePage 10 . Measure contact resistance [R c ] Heat up to burn-in temperature Measure R c Cool down Measure R cUnload Device Restart‣ Optical inspection of contact tips and solder balls

Burn-in Simulation IIBiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003Contact resistance: supplier “A”Contact resistance: supplier “B”Holger HoppePage 11 .

Burn-in Simulation IIIBiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003Contact resistance: supplier “C”* Plating: Gold* Contact shape: SharpContact resistance: supplier “D”Holger HoppePage 12 .* Plating: Gold* Contact shape: Sharp

Burn-in Simulation IVBiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003Contact resistance: supplier “E”* Plating: NiB* Contact shape: SharpContact resistance: supplier “F”Holger HoppePage 13 .* Plating: Rhodium* Contact shape: Standard

Loader/Unloader Simulation IBiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003‣Mechanical Reliability10.000 cover actuation cycles without device or with one device or with device exchange with / without R c measurementSocket actuation force by way chart‣Loader/Unloader simulationdevice shift test: X-/ Y-direction maximum allowed shiftdevice rotation testdevice drop height maximum allowed angel optimumHolger HoppePage 14 .

Loader/Unloader Simulation IIBiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003‣Automated device X-/Y-shift test starting in the center of the socket @ (0;0) short circuit device:Holger HoppePage 15 . align in the presizer load device with growing shift measure R C of all 4 corner pins [Open/Close?] step-by-step shift to all 4 corners unload and back to presizer resolution 0.05 mm; min +/-0.5mm = matrix 21 x 21 repetition with varying angles for device rotation test

Loader/Unloader Simulation IIIBiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003Spiral for X-/Y-ShiftHolger HoppePage 16 .Possible Results for X-/Y-Shift

Loader/Unloader Simulation IVBiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003Engineering field withforce sensorForce sensor block above TSOP66Holger HoppePage 17 .

Loader/Unloader Simulation VBiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003Force by way chart: supplier 1* stroke 2.1 mm* actuation force max 13.9 NForce by way chart: supplier 2Holger HoppePage 18 .* stroke 2.1 mm* actuation force max 17.6 N

Loader/Unloader Simulation VIBiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003Force by way chart: supplier 3* stroke 2.1 mm* actuation force max 15,5 N@ 2.1mmHolger HoppePage 19 .

Loader/Unloader Simulation VIIBiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003Force by way chart: supplier 4* stroke 3.5 mm* actuation force max 19.6 NForce by way chart: supplier 5* stroke 3.5 mm* actuation force 19.6N / max 26.46NHolger HoppePage 20 .

ConclusionsBiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003‣ Simulations approach certain burn-in process conditions‣ Fast way to evaluate and release burn-in sockets‣ Better results for socket life time estimation‣ Better purchasing decision and recommendation‣ Better burn-in socket development together with socket suppliers -- fast customer feedback‣ Fast test of new contact types, plating etc.‣ Direct comparison of different sockets / mechanical principles /contacts / platings etc.Holger HoppePage 21 .

OutlookBiTS Burn-in & Test Socket WorkshopMarch 2-5, 2003‣ Investigation of behavior of Green Packages (TSOP and FBGA) inconventional burn-in sockets‣ Investigation of new plating types (anti-sticking)‣ Investigation of vibration stability of contacts‣ Installation of simple tester - equipment in order to apply realmemory devicesHolger HoppePage 22 .Thank you !

Thermal Testing ofBurn-In SocketsJames ForsterSavithri SubramanyamTexas Instruments,Sensors & Controls, Attleboro, MA2003 Burn-in Test Socket Workshop - March 2-5, 2003Hilton Phoenix East/Mesa HotelMesa, Arizona

Outline• Brief introduction of the problem• Definition of thermal resistance• Theoretical and experimentaltechniques to evaluateperformance• Examples of some experimentalresultsThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 2

Thermal DifficultiesRemember this image from 2001?From paper by Mark Miller titled:Burn-in & Test System for Athlon Microprocessors : Hybrid Burn-in.BiTS Conference Session 5, 2001Thermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 3

Computers and PowerNot a New problemJan 1946 - ENIAC18,000 electron tubes233 sq. metres140 kW30 TonsJan 2000 - Sony8.8 million transistors0.15 sq. metres40W7 lb.Thermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 4

The Problem• As processor speed increases powerincreases• Packages dissipate more power today – willdissipate more power tomorrow• For burn-in socket suppliers - heatgenerated during burn-in of high powerpackages can lead to thermal runawaycausing damage the socket, the board andpotentially the oven or systemThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 5

Some Types of PackagesCeramic LGA with heat spreaderCeramic PGA with heat spreaderCeramic LGA with heat spreaderCeramic LGA NO heat spreaderThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 6

Types of SocketSocket Type:• Open top• ClamshellBoard Mount:• Through hole• CompressionMountThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 7

Types Of SocketOpen TopNo Integral Heat SinkWith Integral Heat SinkThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 8

Types Of SocketClamshell With Integral Heat SinkClamshell for LGACompression MountClamshell for PGAThru-holeThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 9

Thermal Difficulties• Thermal runawayduring burn-in cancause catastrophicfailure.• Defective sockets canbe difficult to remove.• Reduced burn-incapacity.Thermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 10

• HistoricallyBurn-inSystems were “ovens” used to heat thedevices with appropriate controls and systemsfor generating test patterns• Today SystemsOven is an environmental chamberHeat generated by device under testSystem controls temperature of individualdevices on a board to reduce temperaturevariabilityThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 11

Burn-inConventional System - Passive Thermal Control• Indirect heating from air - socket is “Passive”• As air travels through the oven the “ambient”temperature increases• Device in socket 1 experiences different burn-inconditions than devices in sockets 2 or 380°c 85°c90°cSocket 1 Socket 2 Socket 3AIR FLOWThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 12

Burn-inNew System - Active Thermal Control• Direct heating/cooling of each socket.• Each socket/device has individualtemperature monitoring and “Active ThermalControl” to maintain specific temperature.• Cooling/heating of each socket controlled byindividual fans or heaters for each socket.• Temperature uniformity +/- 5 deg.CThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 13

Burn-inActive Thermal Control - MCCV (Fan tray)Cool Air DuctFanV (Socket tray)Burn-in BoardBurn-in SocketMCC HPB-3 SystemThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 14

Burn-inActive Thermal Control - Unisys SystemUnisys STS 3000Thermal Button whichinterfaces with the packageFrom: A Large Capacity and High-Performance Burn-Inand Test System for High-Power Dissipating ComponentsBy Dr. Jerry Tustaniwskyj et al, BiTS Workshop 2002Thermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 15

ConvectionHeat sink to airHeat Transfer MechanismsCeramic Lidded PackageConductionThrough heat sinkInterfacePackage to heat sinkconduction/convectionConductionThrough lid CuW, Al,AlSiC or ?Interface material –conduction/convectionConductionThrough siliconThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 16

Thermal Issues - AnalysisAnalytical/Computational CapabilitiesFEA – Finite Element AnalysisCFD – Computational Fluid DynamicsExperimentalWind TunnelThermal Imaging using infra-red CameraThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 17

Thermal Issues – Heat TransferConduction –Through silicon to surface of package.Well understoodPhysical constantConvection –From heat sink surface to air.Less understoodDependent on many variables.Temperature.Surface finish.Local flow velocityThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 18

Thermal Issues – Heat TransferInterface ResistanceHeat transfer between mating surfaces.Least understood – most variable.- Chip to thermal interface material- Thermal interface material to heat spreader/lid- Package to heat sink- Heat sink to airThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 19

T (Ambient)Temp of airThermal Resistance - θ jaThermal resistance is defined by θ ja(Theta j-a). WhereT (Junction)Temp of Dieθ ja = T junction - T ambientPower– T (Junction) - Temperature of the device,measured by an “on-chip” sensor– T (Ambient) - Temperature of the ambientair.– Power - Power the package isdissipating.Thermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 20

Thermal Testing Standards- EIA /JEDECTest methods for determination of θ ja and otherbasic thermal characteristics:EIA/JEDEC: (Electronic Industries AssociationJoint Electron Device Engineering Council)JESD51: Methodology for the Thermal Measurement of ComponentPackages (Single Semiconductor Device)JESD51-4: Thermal Test Chip Guidelines (Wire-Bond-Type-Chip)JESD51-6: Integrated Circuit Thermal Test Method EnvironmentalConditions – Forced Convention (Moving Air)JESD51-8: Integrated Circuit Thermal test method EnvironmentalConditions – Junction-to-BoardSee:http://www.thermengr.com/tea041.htmlhttp://www.jedec.org/Thermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 21

Thermal Testing Standards- SEMITest methods for determination of θ ja and otherbasic thermal characteristics.SEMI (Semiconductor Equipment and Materials International.):G-30-88: Test Method for Junction-to-Case Thermal Resistancemeasurement for Ceramic packagesG32-094: Guideline for Unencapsulated Thermal Test Chip DesignG42-0996: Specification for Thermal Test Board Standardization forJunction-to-ambient thermal resistance of Semi-ConductorPackageG38-0996: Test Method for Still- and Forced-Air Junction-to-ambient.See: http://www.thermengr.com/tea041.htmlhttp://www.semi.org/PUBS/SEMIPUBS.NSF/92796f5466497e40882565f6000d07af?OpenViewThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 22

Experimental Tools– Wind TunnelProvides a stable, controlled, repeatableenvironment for testing and comparison ofsockets and systems.• Includes flow straightener• Turbulence dampers• Hot wire anemometer• Flow control0 to 2,000 Linear Feet per Minute (LFM)Thermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 23

Wind TunnelThermal Imaging CameraWorking SectionAirflowInletExitThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 24

Thermal Test ChipDescription• A custom semiconductor chip.• Flexible solution which allows the thermalcharacterization of semiconductor packages.• Usually a resistor network which acts as aheater.• Diodes or transistors used as temperaturesensors.• Allows conventional processing of packagethrough all normal packing processes.Thermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 25

Thermal Test ChipSuppliersDelphi:http://delphi.com/automotive/microelectronics/testdie/available/Thermal Engineering Associates:http://www.thermengr.com/tea51.htmlMicred Ltd:http://www.micred.com/index3.htmlThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 26

Thermal Test ChipCalibration• Each temperature sensormust be calibrated.• Simple procedure –Placed in oven at knowntemperatures - resistancemeasured at minimum of4 different temperatures.• Relationship betweentemperature andresistance is linear.• Equation developed foreach sensor.Temperature(C)120100806040200RTD(4) y = 338.05x - 249.09R 2 = 10.75 0.8 0.85 0.9 0.95 1 1.05Resistance (k-ohm)T = 337.62 R - 248.27T - Temp R - ResistanceCorrelation Coeff R 2 = 1Thermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 27

Thermal Test ChipPackagingCeramic LGA packageFlip chip bare dieCeramic LGA packageCu/W lid/heat spreaderThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 28

Thermal Test ChipSize 22*22 mmDie composite of 34 individualdie5*5 Array of thermal die3 Die have smaller 4*4 arrayEach die has resistor and RTDIndividual die heaterresistance 130 ohmsThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 29

Thermal Test Chip1,3 3,31,1 3,1• Initiated thermal testingusing 4 heaters(highlighted in red)• Heaters wired in parallel• Resistance 33 ohms• Easily powered to 50watts.Voltage - 40.62Current – 1.23 ampsThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 30

Experimental Tools– Thermal ImagingAdvantagesBest method for determining temperature fieldsNon contact, Non invasiveProvides pictorial representation of thermalinteraction of different parts of the socketFull field visibility – not temperature of adiscrete pointDifficultiesEmissivity of different surfaces and materials.Thermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 31

ExampleTemperature Distribution on PackageObjective:Method:Evaluate temperature distributionin die due to use of 4 modulesCompare results for the lidded andlidless (bare die)Modify burn-in socket to providewindow to package.Paint socket and package with flatblack paint to eliminate emissivityproblems.Thermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 32

ResultsOriginal Socket for Ceramic LGAThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 33

ResultsSocket Modifications – Lidded PackageThe central area of the heat sinkwas removed so that the lid of thepackage is visible.Note flat black paint on CuW lidThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 34

ResultsThermal Image Lidded Package - No PowerHeat loss by conductioninto socket and naturalconvection.No air flow over socketNo PowerNote uniformity of temperatureThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 35

ResultsThermal Image - Lidded Package – 2.9 WattsImage demonstratesuniform temperatureon lidTemperature on Package Lid39.5 +/- 1°CThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 36

ResultsThermal Image - Lidless Package – No PowerTemperature on Lid+/- 0.6°CThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 37

ResultsThermal Image Lidless Package – 3.0 WattsSlot in frame for heaterHoles for shoulder screwDie Temperature42 +/- 2.0°CThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 38

RESULTSComparison of FEA versus Wind Tunnel TestingFEA Prediction ½ model of heat sink on flip chip bare diePredicted θja – 3.0 °C/watt Actual 3.2°C/wattThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 39

ResultsExperimental Thermal Image of Heat Sink• Comparison of thermal images for:a) lidded and b) bare die package.• Both images indicate that impinging air keeps “forward”heat sink cooler.a) b)Air FlowThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 40

ExampleUse of Thermal Imaging to Resolve ProblemWind tunnel test results on open top socketindicated θja was higher than predicted.Use of thermal imaging helpedprovide insight to solveproblem (see next slide)–Poor contact between heatsink and package.–Mechanism not functioningproperly.Thermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 41

ExampleUse of Thermal Imaging to Resolve ProblemPoor contact between heat sink and packageInitial resultθja – 4.4 °C/wattAfter modificationθja – 3.1 °C/wattThermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 42

Conclusions/Summary• Analytical tools such as FEA and simpleanalyses reduce socket design cycle timeand cost by allowing evaluation of differentconcepts before cutting metal.• Experimental tools such as the wind tunneland infra-red thermography provide• confirmation of basic assumptions.• visual records of the actual testconditions and insight into the thermalpath and heat flow.Thermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 43

AcknowledgementsWork presented here was the result of mucheffort by many people.The authors gratefully acknowledge thework by the following: …….• Design Teams in USA, Japan and Korea.• Manufacturing Teams in Japan, andKorea• Technical Services and Thermal TestLab.Thermal Testing of Burn-in Sockets – Forster et al. BiTS Workshop, Phoenix, Az March 2 - 5, 2003 44