Rabbit 2000™ Microprocessor - UTN

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The cold boot mode and the triplets sent are described in Section 4.1 on page 20. Each triplet consistsof a 2-byte address and a 1-byte data value. The data value is stored in the address specified.The uppermost bit of the 16-bit address is set to one to specify an internal I/O write. The remaining15 bits specify the address. If the write is to memory then the uppermost bit must be zero andthe write must be to the first 32k of the memory space. The user should see the 9 bytes transmittedat 2400 bps or 416 µs per bit. The status bit will initially toggle fairly rapidly during the transmissionof the first triplet because the default setting of the status bit is to go low on the first byte ofan opcode fetch. While the triplets are being read instructions are being executed from the smallcold boot program within the microprocessor. The status line will go low after the first triplet hasbeen read. It will go high after the second triplet is finished. It will return to low again after the 3rdtriplet is transmitted. and stay that way until the sequence starts again.If this test fails to function it may be that the programming connector is connected improperly orthe proper pull-up resistors are not installed on the SMODE lines. Other possibilities are that oneof the oscillators is not working or is operating at the wrong frequency. The reset could be failing.12.3 Diagnostic Test #3This test checks the functioning of the RAM connected to /CS1/OE1/WE1. The test applies thereset, then sends a series of triplets to set up the necessary control registers. Then it writes severalinstructions to RAM. Finally it begins executing instructions in RAM. These instructions disablethe watchdog timer.80 14 05 //set MB0CR to 1 to select RAM80 09 51 //ready watchdog for disable80 09 54 //disable watchdog timer//sequence of triplets to write program below to memory// starting at address zero.00 01 2100 02 0100 03 0000 04 0600 05 1000 06 7e00 07 2900 08 1000 09 FC00 0A C300 0B 0060 <strong>Rabbit</strong> 2000 <strong>Microprocessor</strong>
80 24 80 //terminate bootstrap, start at address zero;test programld hl,1ld b,16loop:ld a,(hl)add hl,hl ; shift leftdjnz loop ; 16 stepsjp 0 ; continue testIf this test runs it will toggle the first 16 address lines. In addition, all of the data lines must befunctioning or the program would not execute correctly.Designer’s Handbook 61
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Rabbit 2000 MicroprocessorDesigner
Page 3 and 4:
Table of Contents1 Introduction ...
Page 5 and 6:
Instructions Affected by the Wait S
Page 7 and 8:
1. IntroductionThis manual is inten
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2. Rabbit Hardware DesignOverviewBe
Page 11 and 12:
2.3 Power ConsumptionWhen minimum p
Page 13 and 14:
3. Core Design and ComponentsCore d
Page 15 and 16: 3.2 Basic Memory DesignNormally /CS
Page 17 and 18: 3.3 PC Board Layout and Memory Line
Page 19 and 20: With a Rabbit-based system it is ea
Page 21 and 22: 3.4.2.3 High Frequency Oscillator C
Page 23 and 24: 3.4.2.4 Processor DecouplingThe int
Page 25 and 26: 4. How Dynamic C Cold Boots theTarg
Page 27 and 28: 4.2 Program Loading Process Overvie
Page 29 and 30: 5. Rabbit Memory OrganizationThe Ra
Page 31 and 32: 5.2.1 DefinitionsExtended Code: Ins
Page 33 and 34: 5.3.2 Paged Access in Extended Memo
Page 35 and 36: 6. The Rabbit BIOSWhen Dynamic C co
Page 37 and 38: 6.2 BIOS FlowchartThe following flo
Page 39 and 40: DATAORGBeginning logical address fo
Page 41 and 42: All origin statements must have a u
Page 43 and 44: 7. The System ID BlockThe BIOS supp
Page 45 and 46: 7.2 AccessThe BIOS will read the sy
Page 47 and 48: Table 4. The System ID Block (Conti
Page 49 and 50: 8. BIOS Support for ProgramCloningT
Page 51 and 52: 8.2.3 LED PatternsThe following tab
Page 53 and 54: 9. Low-Power Design and SupportTo g
Page 55 and 56: 9.1 Software Support for Low-Power
Page 57 and 58: 10. Memory PlanningThe following re
Page 59 and 60: 11. Flash MemoriesThe flash memorie
Page 61 and 62: Table 7. 32-Pin Flash Memories Supp
Page 63 and 64: The field flashXPC contains the XPC
Page 65: 12. Troubleshooting Tips for NewRab
Page 69 and 70: Appendix A. Supported Rabbit 2000Ba
Page 71 and 72: Appendix B.Wait State BugB.1 Overvi
Page 73 and 74: If the atomic nature of the operati
Page 75 and 76: B.4 Enabling Wait StatesMemory wait
Page 77: Legal NoticeRabbit Semiconductor pr
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