ST7565 - Topwaydisplay.com

ST7565The Display Data Latch CircuitThe display data latch circuit is a latch that temporarilystores the display data that is output to the liquid crystaldriver circuit from the display data RAM.Because the display normal/reverse status, display ON/OFFstatus, and display all points ON/OFF commands controlonly the data within the latch, they do not changethe data within the display data RAM itself.The Oscillator CircuitThis is a CR-type oscillator that produces the display clock.The oscillator circuit is only enabled when M/S= “H” andCLS = “H”.When CLS = “L” the oscillation stops, and the externalclock is input through the CL terminal.Display Timing Generator CircuitThe display timing generator circuit generates the timingsignal to the line address circuit and the display data latchcircuit using the display clock. The display data is latchedinto the display data latch circuit synchronized with thedisplay clock, and is output to the data driver output terminal.Reading to the display data liquid crystal driver circuits iscompletely independent of accesses to the display dataRAM by the MPU. Consequently, even if the display dataTwo-frame alternating current drive waveformRAM is accessed asynchronously during liquid crystaldisplay, there is absolutely no adverse effect (such asflickering) on the display.Moreover, the display timing generator circuit generates thecommon timing and the liquid crystal alternating currentsignal (FR) from the display clock. It generates a drive waveform using a 2 frame alternating current drive method, as isshown in Figure 5, for the liquid crystal drive circuit.Figure 5Ver 0.9 17/17 2001/01/11