Carbon L2CC PL310 Model User Guide for SoC Designer

1-6 Using the Model Component in SoC Designer PlusTable 1-2 ESL Component Ports (Continued)ESL Port Description Direction TypeINCLKENM1/OUTCLKENM1INCLKENS0/OUTCLKENS0INCLKENS1/OUTCLKENS1Clock enable for input/output clocks forport axi_m1Clock enable for input/output clocks forport axi_s0Clock enable for input/output clocks forport axi_s1InputInputInputREGFILEBASE Register file base address Input intSPNIDEN Bypass security for output events Input boolTAGCLKEN 2. Clock enable for tag RAM interface Input boolTAGRAMCLK 2. Clock for tag RAM, see also TAGCLKEN Input clockWAYSIZE 1. Cache way size Input intaxi_m0 AXI master port 0 Master AXIaxi_m1 AXI master port 1 Master AXIIDLE Notify PL310 is idle Output boolDATAWRITELAT Write data RAM latency Output intDATAREADLAT Read data RAM latency Output intCO Cast out (line eviction) event Output boolDRHIT Data read hit event Output boolDRREQ Data read miss event Output boolDWHIT Data write hit event Output boolDWREQ Data write-back miss event Output boolDWTREQ Data write-through miss event Output boolIRHIT Instruction read hit event Output boolIRREQ Instruction read miss event Output boolWA Write allocation Output boolDECERRINTR 3 Imprecise DEC error interrupt Output boolSLVERRINTR 3. Imprecise SLV error interrupt Output boolECNTRINTR 3. Configurable event interrupt Output boolL2CCINTR 3. Global interrupt Output bool1. These input values are only taken into account after reset.2. Available only if user defined RAM clock enable option was selected.See the section on“RAM clocking” in the ARM PrimeCell Level 2 Cache Controller (PL310 Technical ReferenceManual for more details on how to drive these inputs.3. For these interrupt ports, the active high/low setting is controlled by the negLogic componentparameter. The default is active high.intintintCarbon Design Systems, Inc. Confidential