Porosity Aware Buffered Steiner Tree Construction - Computer ...

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. XX, NO. Y, MONTH 2003 101000000000111111111000000000111111111000000000111111111000000000111111111000000000111111111Sink000000000011111111110000000000111111111100000000001111111111000000000011111111110000000000111111111100000000001111111111000000000011111111110000000000111111111100000000001111111111Buffer(a)SinkSource00000000111111110000000011111111000000001111111100000000111111110000000011111111SinkSink000000000001111111111100000000000111111111110000000000011111111111000000000001111111111100000000000111111111110000000000011111111111000000000001111111111100000000000111111111110000000000011111111111Buffer(b)SourceFig. 2. An arbitrary Steiner tree as shown in (a) may force wires to passthrough routing congested regions. A congestion aware buffered Steiner tree,which is shown in (b), will may let wires go through sparse regions.B. The Importance of PorosityIn tradition design flows, buffer insertion is applied afterplacement to optimize interconnect timing. As interconnecteffects become increasingly severe, buffer insertion needs to bepushed up earlier in the design flow to help logic optimizationand placement algorithms on interconnect estimation and toreserve buffering resources. The sheer number of nets thatrequire buffering means that resources need to be allocatedintelligently. For example, large blocks placed close togethercreate narrow alleys that are magnets for buffers since theyare the only locations that buffers can be inserted for routesthat cross over these blocks. But competition for resources forthese routes is very fierce. Inserting buffers for less criticalnets can eliminate space that is needed for more critical netsthat may require gate sizing or other logic transforms. Further,though no blockages lie in the alleys, these regions couldalready be packed with logic and no feasible space for thebuffer might exist. If the buffer insertion algorithm cannotrecognize this scenario then inserting a buffer into this spacemay cause placement legalization to spiral it out to a regiontoo far from its original location. Hence, whenever possibleone should avoid denser regions unless absolutely critical.For example, Figure 1(a) shows a net which is routedthrough a dense region or “hot spot”, and Figure 1(b) showsthe net routed differently to avoid this congested region.In addition to porosity (or placement congestion), a buffersolution may generate remarkable impact on wiring congestionas well. Figure 2 (a) and (b) show an example for a multi-pinnet where the Steiner point needs to be moved outside of thedense region to yield less wiring congestion.The literature contains no buffering approach which addressesthese issues. Note that several algorithms (such asS-Tree and SP-Tree) could be used to address porosity constraintssince they can be run on arbitrary grid graphs. However,the extensions are hardly straightforward. One has tocarefully consider the weighting scheme for edges in the gridgraph, how to sparsify the graph to give reasonable runtimes,the appropriate cost functions, etc. Further, any simultaneousapproach is likely to require too much runtime to be practicallyused within physical synthesis.This work proposes a porosity aware buffered Steiner treeconstruction and is the first buffer insertion work to addressporosity in the layout directly (as opposed to simply specifyinga handful of allowable buffer insertion locations). Theapproach begins with a timing-driven but porosity-ignorantSteiner tree, then applies a plate-based adjustment guidedby length based buffer insertion. After performing localizedblockage avoidance, the resulting tree is then passed to vanGinneken’s algorithm to obtain a porosity aware bufferedSteiner tree. Physical synthesis experiments on real industrialcircuits confirms the effectiveness of this framework.II. PROBLEM FORMULATIONThe porosity is represented through a tile graph G(V G ,E G )where a node g ∈ V G corresponds to a tile and an edge e uv ∈E G represents a boundary between two neighboring tiles uand v ∈ V G . A high porosity implies a low congestion ordensity, vice versa. If a tile g ∈ V G has an area of A(g)and its area occupied by placed cells are a(g), the placementdensity is defined as the area usage density d(g) = a(g)A(g)oftile g. For the boundary between two adjacent tiles g i andg j , its wire density d(g i ,g j ) is the number of wires across itdivided by the number of wiring tracks across this boundary.We take d 2 (g i ,g j ) as wire density cost in our implementation.We address the following problem:Porosity-aware Buffered Steiner Tree Problem: Givena net N = {v 0 ,v 1 ,...,v n } with source v 0 and sinks{v 1 ,...,v n }, load capacitance c(v i ) and required arrival timeq(v i ) for 1 ≤ i ≤ n, tile graph G(V G ,E G ), and a buffer type b,construct a Steiner tree T (V,E), in which V = N ∪ V Steinerand edges in E span every node in V , such that a bufferinsertion solution that satisfies q(v i ) may be obtained with aminimal porosity cost(wire density cost).For porosity cost, one can sum the costs of the tiles that theroutes cross. We use the following function, though certainlyothers can be used as well, depending on the application. Foreach buffer inserted in a tile g, the porosity cost p(g) is definedas:⎧⎨0.5 : d(g) ≤ 0.5p(g) = 4d 2 (g) − 2d(g)+0.5 : 0.5
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. XX, NO. Y, MONTH 2003 102SourceSourcev1v5v1v5v1v5v4v3v4v3v4v3v2v2v2(a)(b)(c)Fig. 3. (a) Candidate solutions are generated from v 2 and v 3 and propagated to every tile, which is shaded, in the plate for v 4 . Solution search is limitedto the bounding boxes indicated by the thickened dashed lines. (b) Solutions from v 1 and every tile in the plate for v 4 are propagated to the plate for v 5 . (c)Solutions from plate of v 5 are propagated to the source and the thin solid lines indicate an alternative tree that may result from this process.a van Ginneken style buffer insertion algorithm that employshigher order delay models, handles slew and load capacitanceconstraints, manages a library of inverting and non-invertingbuffers and trades off buffer resource utilization with solutionquality. Integrating a Steiner tree construction into this algorithmwhile maintaining all its features would be prohibitive.However, just constructing a Steiner tree without performingbuffer insertions cannot possibly yield the best topology.Therefore, we propose to solve the porosity aware bufferedSteiner tree problem through the following four stages:1) Initial porosity ignorant timing-driven Steiner tree construction2) Plate-based adjustment for porosity improvement3) Local blockage avoidance4) Van Ginneken style buffer insertionFor stage one, one can construct a timing-driven Steiner treethrough any heuristics. We choose to apply the “buffer aware”C-Tree algorithm [3]. The C-Tree algorithm first clusters thesinks according to their timing criticality, signal polarity andlocation proximity. Then a timing driven Steiner tree algorithmis applied to obtain the intra-cluster and inter-cluster routings.Stage 2 contains the key ideas behind the algorithm. Theplate-based adjustment phase modifies the existing timingdrivenSteiner in an effort to reduce congestion cost whilemaintaining the tree’s high performance. One of the key elementsis that it allows Steiner points to migrate outside of highporositytiles into lower-porosity tiles to reduce congestionwhile maintaining (if not improving) performance.After Stage 2, the Steiner tree is correct in that it goesthrough the tiles that optimize performance while minimizingporosity cost, though the routes may overlap blockages. Performinglocal blockage avoidance in Stage 3, manipulates theroutes within each tile to avoid blockages, thereby allowingmore buffer insertion candidates. However, this stage does notdisturb the tree topology uncovered from Stage 2.Finally, in Stage 4 the resulting tree topology is fixed for vanGinneken style buffer insertion [16]. Van Ginneken’s algorithmis a dynamic programming based bottom-up approach. A setof candidate solutions are propagated from leaf nodes towardthe source and the optimal solution is selected at the source.Since we use known algorithms for Stages 1 and 4, the restof the discussion focuses on the other two stages.B. Stage 2: Plate-based AdjustmentsThe basic idea for the plate-based adjustment is to perform asimplified simultaneous buffer insertion and local tree adjustmentso that the Steiner nodes and wiring paths can be movedto regions with greater porosity without significant disturbanceon the timing performance obtained in Stage 1.The buffer insertion scheme employed here is similar to thelength based buffer insertion in [2]. However, we allow theSteiner points and wiring paths to be adjusted. This approachis also distinctive from a simultaneous buffer insertion andSteiner tree construction approach [14] in which the Steinertree is built from scratch. The plate-based adjustment traversesthe given Steiner topology in a bottom-up fashion similar tovan Ginneken’s algorithm. During this process, Steiner nodesand wiring paths may be adjusted together with buffer insertionto generate multiple candidate solutions.The range of the moves are restrained by the plates definedas follows. For a node v i ∈ T (V,E) which is located in a tileg k ,aplate P (v i ) for v i is a set of tiles in the neighborhood ofg k including g k itself. During the plate-based adjustment, weconfine the location change for each Steiner node within itscorresponding plate. If v i is a sink or the source node we letP (v i )={g k }. For example, when v i is a branch node, we setP (v i ) to be the 3 × 3 array of tiles centered at g k . Of course,if g k lies on the border of the entire tile graph, P (v i ) mayinclude fewer tiles. Figure 3(a) gives an example of the platecorresponding to Steiner node v 4 . The plate indicates any ofthe possible location which the Steiner node may be movedto. This example shows the Steiner node being moved up onetile and right one tile.The search for alternate wiring paths is limited to theminimum bounding box covering the plates of two endnodes. In Figure 3, such bounding boxes are indicated by thethickened dashed lines. Therefore, the size of plates definethe search range for both Steiner nodes and wiring paths.
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