Logic Synthesis with VHDL System Synthesis Bob Reese Electrical ...

Logic Synthesis with VHDLSystem SynthesisBob ReeseElectrical Engineering DepartmentMississippi State University

Electrical & Computer EngineeringMississippi State UniversityVHDL Packages⇒ A VDHL package is a mechanism for collecting procedures, functions,constants, and components for future re–use.⇒ A package contains a package declaration followed by a packagebody.→ Package declarationpackage package_name is{ external constant, procedure, function,component declarations }end package_name;→Package bodypackage body package_name is{constant, procedure, function, componentdefinitions }end package_name;⇒ Any items in the package declaration are available for externaluse. There can be items in the package body which are not in thepackage declaration; these items are only available for use withinthe package.Bob Reese 5/95System–2System Design with VHDL

Electrical & Computer EngineeringMississippi State UniversityExample VHDL PackageLibrary IEEE; use IEEE.std_logic_1164.all;package iscas isprocedure ripple_adder (a,b: in std_logic_vector; cin: in std_logic;sum: inout std_logic_vector; cout: out std_logic);end iscas;package body iscas isfunction xor3 (a,b,c: in std_logic) return std_logic isbeginreturn (a xor b xor c);end xor3;procedure ripple_adder (a,b: in std_logic_vector; cin: in std_logic;sum: inout std_logic_vector; cout: out std_logic) isvariable c: std_logic_vector((a’high–a’low+1) downto 0);beginc(0) := cin;for i in 0 to (a’high–a’low) loopsum(i+sum’low) := xor3 (a(i+a’low), b(i+b’low), c(i) );c(i+1) := (a(i+a’low) and b(i+b’low)) or(c(i) and (a(i+a’low) or b(i+b’low)));end loop;cout := c(c’high);end ripple_adder;end iscas;Bob Reese 5/95System–3System Design with VHDL

Electrical & Computer EngineeringMississippi State UniversityVHDL Functions⇒ General form:function function_name ( parameter list) return return_type is{variable declarations}begin{sequential statements}end function_name;function xor3 (a,b,c: in std_logic) return std_logic isbeginreturn (a xor b xor c);end xor3;⇒ A VHDL function computes a return value based upon its parameterlist.→ All parameters passed to a VHDL function must be of mode in;i.e, the function is not allowed to modify any of the functionparameters.→ The default class of the elements in a parameter list for eitherprocedures or functions is variable.→ Signals can be passed in the parameter list; in this case theparameter list would look like:(signal a, b, c: std_logic)→ More on the difference between variables and signals will begiven later.Bob Reese 5/95System–4System Design with VHDL

Electrical & Computer EngineeringMississippi State UniversityVHDL Procedures⇒ General form:procedure procedure_name ( parameter list) is{variable declarations}begin{sequential statements}end procedure_name;⇒ The ripple_adder procedure implements the ripple carry adderused in previous examples.⇒ The ripple_adder procedure uses the local xor3 function definedwithin the package.sum(i+sum’low) := xor3 (a(i+a’low), b(i+b’low), c(i) );⇒ For generality, the input parameters ’a’ and ’b’ as well as the output’sum’ are declared as unconstrained array types; i.e., no arraybounds are given for the std_logic_vector type.→ Allows any width vector to be passed as a parameter.→ Array indices must be computed using the ’low attribute as anoffset in order to achieve independence from the actual arrayindices which are passed in.Bob Reese 5/95System–5System Design with VHDL

Electrical & Computer EngineeringMississippi State UniversitySignals vs Variables⇒ Only signals are used as the connection ports for VHDL entities.→ Variables are declared within process blocks, procedures,and functions.→ Signals can only be declared within architecture bodies; theycan be passed as parameters to functions and procedures.⇒ Signals are assigned via ”

Electrical & Computer EngineeringMississippi State UniversityUsing the ripple_adder ProcedureLibrary IEEE;use IEEE.std_logic_1164.all;use work.iscas.all;entity adder_test isport (signal a,b: in std_logic_vector (15 downto 0);signal cin: in std_logic;signal sum: out std_logic_vector(15 downto 0);signal cout: out std_logic);end adder_test;architecture behavior of adder_test isbeginprocess (a,b,cin)variable temp_sum: std_logic_vector (sum’range);variable temp_cout: std_logic;beginripple_adder(a, b, cin, temp_sum, temp_cout);sum

Electrical & Computer EngineeringMississippi State UniversityA Carry Select AdderK bitsCIASUMBCOUTSUMEach stage computes part of thesum. Typically, the stage sizes increase;so a 16 bit adder stagesizes might be 4, 5, 7 = total of16 bits. Ripple adders are usedfor stage adders.CS001L bitsCIASUMBCOUTCIASUMBCOUT01MUXSUMCS001CS1M bitsCIASUMBCOUTCIASUMBCOUT01MUXSUMCS1CS2....... etc.Bob Reese 5/95System–8System Design with VHDL

Electrical & Computer EngineeringMississippi State UniversityCarry_Select_Adder Procedureprocedure carry_select_adder(groups: iarray; a,b: in std_logic_vector; cin: in std_logic;sum: inout std_logic_vector; cout: out std_logic) isvariable low_index, high_index :integer;variable temp_sum_a, temp_sum_b : std_logic_vector(sum’range);variable carry_selects :std_logic_vector(groups’range);variable carry_zero :std_logic_vector(groups’low to (groups’high–1));variable carry_one :std_logic_vector(groups’low to (groups’high–1));beginlow_index := 0;for i in groups’low to groups’high loophigh_index := (groups(i)–1) + low_index ;if (i = 0) then –– first group, just do one ripple–carryripple_adder (a(high_index downto low_index), b(high_index downto low_index),cin, sum(high_index downto low_index), carry_selects(0) );else–– need to do two ripple carry adders then use mux to selectripple_adder (a(high_index downto low_index), b(high_index downto low_index),’0’, temp_sum_a(high_index downto low_index), carry_zero(i–1));ripple_adder (a(high_index downto low_index), b(high_index downto low_index),’1’, temp_sum_b(high_index downto low_index), carry_one(i–1));if (carry_selects(i–1) = ’0’) thensum(high_index downto low_index) := temp_sum_a(high_index downto low_index);elsesum(high_index downto low_index) := temp_sum_b(high_index downto low_index);end if;carry_selects(i) := (carry_selects(i–1) and carry_one(i–1) ) or carry_zero(i–1);end if;low_index := high_index + 1;end loop;cout := carry_selects(groups’high);end ripple_adder;Bob Reese 5/95System–9System Design with VHDL

Electrical & Computer EngineeringMississippi State Universityiscas Package DeclarationLibrary IEEE;use IEEE.std_logic_1164.all;package iscas istype IARRAY is array (natural range ) of integer;procedure ripple_adder (a,b: in std_logic_vector; cin: in std_logic;sum: inout std_logic_vector; cout: out std_logic);procedure carry_select_adder(groups: iarray; a,b: in std_logic_vector; cin: in std_logic;sum: inout std_logic_vector; cout: out std_logic);end iscas;⇒ We need to declare an array type for integers; call this IARRAY.This type will be used to pass in an integer array to the carry_select_adderprocedure; the integer array will be define the stagesizes for the adder.⇒ Since xor3 is to be local to the iscas package; it is not in the packagedeclaration. However, if it was to be made externally available,its declaration would be:function xor3 (a,b,c: in std_logic) return std_logic;Bob Reese 5/95System–10System Design with VHDL

Electrical & Computer EngineeringMississippi State UniversityUsing the carry_select_adder ProcedureLibrary IEEE;use IEEE.std_logic_1164.all;use work.iscas.all;entity adder_cs isport (signal a,b: in std_logic_vector (15 downto 0);signal cin: in std_logic;signal sum: out std_logic_vector(15 downto 0);signal cout: out std_logic);end adder_cs;architecture behavior of adder_cs isbeginprocess (a,b,cin)variable temp_sum: std_logic_vector (sum’range);variable temp_cout: std_logic;constant groups: iarray(0 to 2) := (4,5,7);begincarry_select_adder(groups,a,b,cin,temp_sum, temp_cout);sum

Electrical & Computer EngineeringMississippi State University1 2 3 4 5 6 7 81 2 3 4 5 6 7 8ABCDcinA1215411004119101210231214BCD652145621101281314897312151001961014814861411138151510151239845111373115732a(4)a(6)a(1)a(7)a(11)a(12)a(12)a(8)a(13)a(14)n1042813144893210a(15:0)a(15:0)n1044n1038n1031n1024n1018n1011n1027b(15:0)b(6)a(6)n1065n1016sum(6)0019236612756n1035b(7)b(11)n1043n1040n1041n1039n993 n1034sum(7)n1033a(7)n1037n1036b(7)7n1028n1029n1055 n1026sum(11)n1025a(11)n1030b(11)a(12)n1063b(12) n1022sum(12)n1023n1020b(15:0)n1021n1019n1057 n10131112n1015sum(13)n1012a(13)n1017b(13)n1060a(14)a(14) b(14) n1009b(14) n1062 n1010sum(14)n1061n1008n1007b(14)a(9) a(0) sum(0)n1005b(0)b(9)a(10)b(10)13140n997n958b(5)n1004sum(15:0)n1032n1053n994b(8)n984n1058n1059b(4)n1000a(10) sum(10)b(10)n1054 n976n974n1001n975b(0) n1056cin b(12) n973n965b(0)a(0)b(10)a(10)b(1) a(9)n966 sum(15)a(1) n1047n999b(1) n1048 n983b(2) n985a(2)b(12)n1014 a(1) sum(1)n991b(13)b(1)b(2) b(3)n967a(2) a(3)a(2)b(3) n988n968 b(2) sum(2)a(3)b(8)a(3) sum(3)n987b(8) b(3)a(8)n962a(5)n1006n1049n969 n996 sum(9)n964b(9) a(9)b(6) n1052n998b(5)n972n971a(6) n995a(8) n1064 sum(8)n961b(6) a(8)n977 n1002n980n981n979n970sum(4)a(4)n1046b(4)a(5)n1051n1003n1050n982sum(5)n1045n992n978n963n960n959n990n989n986b(15)n957a(15)a(15)b(15)coutsum(15:0)coutBob Reese 5/95System–12System Design with VHDL

Electrical & Computer EngineeringMississippi State UniversityVHDL Generic listsLibrary IEEE;use IEEE.std_logic_1164.all;use work.iscas.all;entity adder_test isgeneric ( N : integer := 16);port (signal a,b: in std_logic_vector (N–1 downto 0);signal cin: in std_logic;signal sum: out std_logic_vector(N–1 downto 0);signal cout: out std_logic);end adder_test;architecture behavior of adder_test isbeginprocess (a,b,cin)variable temp_sum: std_logic_vector (sum’range);variable temp_cout: std_logic;beginripple_adder(a, b, cin, temp_sum, temp_cout);sum

Electrical & Computer EngineeringMississippi State UniversityVHDL Generic lists (cont.)⇒ VHDL generic lists are used in entity declarations for passing staticinformation.→ Typical uses of generics are for controlling bus widths, featureinclusion, message generation, timing values.⇒ A generic will usually have a specified default value; this value canbe overridden via VHDL configurations or by vendor–specificback–annotation methods.→Generics offer a method for parameterizing entitydeclarations and architectures. Because the method ofspecifying generic values (other than defaults) can bevendor specific, generics will not be covered further in thistutorial.Bob Reese 5/95System–14System Design with VHDL

Electrical & Computer EngineeringMississippi State UniversityOperator OverloadingLibrary IEEE; use IEEE.std_logic_1164.all;package genmux is–– 2/1 version, 1 bit inputsfunction mux (a,b: std_logic; sel: std_logic) return std_logic;–– 2/1 version, N bit inputsfunction mux (a,b: std_logic_vector; sel: std_logic) return std_logic_vector;–– 3/1 version, 1 bit inputsfunction mux (a,b,c: std_logic; sel: std_logic_vector) return std_logic;–– 3/1 version, N bit inputsfunction mux (a,b,c: std_logic_vector; sel: std_logic_vector) return std_logic_vector;–– 4/1 version, 1 bit inputsfunction mux (a,b,c,d: std_logic; sel: std_logic_vector) return std_logic;–– 4/1 version, N bit inputsfunction mux (a,b,c,d: std_logic_vector; sel: std_logic_vector) return std_logic_vector;end genmux;package body genmux isfunction mux (a,b: std_logic; sel: std_logic) return std_logic isvariable y: std_logic;beginy := a;if (sel = ’1’) then y := b; end if;return(y);end mux; –– 2/1 version, 1 bit inputsfunction mux (a,b: std_logic_vector; sel: std_logic) return std_logic_vector isvariable y: std_logic_vector(a’range);beginy := a;if (sel = ’1’) then y := b; end if;return(y);end mux; –– 2/1 version, N bit inputsBob Reese 5/95System–15System Design with VHDL

Electrical & Computer EngineeringMississippi State UniversityOperator Overloading (cont.)function mux (a,b,c: std_logic; sel: std_logic_vector) return std_logic isvariable y: std_logic;beginy := ’–’; –– Don’t care for default stateif (sel = ”00”) then y := a; end if; if (sel = ”01”) then y := b; end if;if (sel = ”10”) then y := c; end if;return(y);end mux; –– 3/1 version, 1 bit inputsfunction mux (a,b,c: std_logic_vector; sel: std_logic_vector) return std_logic_vector isvariable y: std_logic_vector(a’range);beginy := (others => ’–’); –– Don’t care for default stateif (sel = ”00”) then y := a; end if; if (sel = ”01”) then y := b; end if;if (sel = ”10”) then y := c; end if;return(y);end mux; –– 3/1 version, N bit inputsfunction mux (a,b,c,d: std_logic; sel: std_logic_vector) return std_logic isvariable y: std_logic;beginy := d;if (sel = ”00”) then y := a; end if; if (sel = ”01”) then y := b; end if;if (sel = ”10”) then y := c; end if;return(y);end mux; –– 4/1 version, 1 bit inputsfunction mux (a,b,c,d: std_logic_vector; sel: std_logic_vector) return std_logic_vector isvariable y: std_logic_vector(a’range);beginy := d;if (sel = ”00”) then y := a; end if; if (sel = ”01”) then y := b; end if;if (sel = ”10”) then y := c; end if;return(y);end mux; –– 4/1 version, N bit inputsend genmux;Bob Reese 5/95System–16System Design with VHDL

Electrical & Computer EngineeringMississippi State UniversityTest of ’mux’ FunctionLibrary IEEE;use IEEE.std_logic_1164.all;use work.genmux.all;entity muxtest isport (signal a,b,c: in std_logic;signal s_a: in std_logic_vector(1 downto 0);signal y: out std_logic;signal j,k,l: in std_logic_vector(3 downto 0);signal s_b: in std_logic_vector(1 downto 0);signal z: out std_logic_vector(3 downto 0));end muxtest;architecture behavior of muxtest isbeginy

Electrical & Computer EngineeringMississippi State UniversityABCD1 2 3 4 5 6 7 8s_a(1:0)s_a(1:0)012s_b(1:0)s_b(0) 0n149z(3) 3s_b(1) 1n150n161n163s_b(0) 01 2 3 4 5 6 7 8ABCD1k(3:0)k(3:0)j(3:0)j(3:0)l(3:0)bl(3:0)abn164 yayccs_a(1)n157s_a(0) 0s_a(0) 0n158n1590 k(0)n1600j(0)n155z(0)0l(0)n156k(1) 11j(1)n153z(1)1l(1)n154k(2) 2z(3:0)2j(2)n151z(2)2l(2)n152k(3) 3s_b(1:0)3 j(3)n162z(3:0)3l(3)Bob Reese 5/95System–18System Design with VHDL

Electrical & Computer EngineeringMississippi State UniversityBlackJack Dealer Control (cont)TESTCancel ACE=11Fscore16gtTMUX: Select SUB10REG: Load scoreF→ace11flag.outscore21gtFTace11flagFTT→stand.outT→broke.outScore is > 16 and< 21 so standScore > 21 and wecan’t adjust anACE value so weare brokeTo GET stateBob Reese 5/95System–21System Design with VHDL

Electrical & Computer EngineeringMississippi State UniversityBlackJack Datapath+105clearCard Switches4–1055MUX255ADDER 5 ScoreREG5selAce Finderacecardscoreloadace11flag.outace11flagMiscellanous Flip Flops tobe included in Control5Comparatorscore16gtscore21gtCardRdybuttoncard.rdy.syncstand.outstandcard.rdy.delaybroke.outbrokeBob Reese 5/95System–22System Design with VHDL

Electrical & Computer EngineeringMississippi State UniversityVHDL File for BlackJack Datapath (cont.)–– adder process–– adder_out

Electrical & Computer EngineeringMississippi State UniversityVHDL File for BlackJack Controlentity bjcontrol is port (signal clk, reset_b, card_rdy, acecard: in std_logic;signal score16gt, score21gt: in std_logic;signal hit, broke, stand: out std_logic;signal sel: out std_logic_vector(1 downto 0);signal score_clear_b, score_load: out std_logic); end bjcontrol;Entity declarationarchitecture behavior of bjcontrol is and State Assignments–– declare internal signals heresignal n_state, p_state : std_logic_vector(1 downto 0);signal ace11flag_pstate, ace11flag_nstate: std_logic;signal broke_pstate, broke_nstate: std_logic;signal stand_pstate, stand_nstate: std_logic;signal card_rdy_dly, card_rdy_sync: std_logic;–– state assignments are as followsconstant get_state: std_logic_vector(1 downto 0) := B”00”;constant add_state: std_logic_vector(1 downto 0) := B”01”;constant test_state: std_logic_vector(1 downto 0) := B”10”;constant use_state: std_logic_vector(1 downto 0) := B”11”;constantconstantconstantadd_10_plus: std_logic_vector(1 downto 0) := B”00”;add_card: std_logic_vector(1 downto 0) := B”01”;add_10_minus: std_logic_vector(1 downto 0) := B”10”;Bob Reese 5/95System–25System Design with VHDL

Electrical & Computer EngineeringMississippi State UniversityVHDL File for BlackJack Control (cont.)begin–– state process to implement flag flip–flops and FSM statestate: process(clk, reset_b)beginif (reset_b = ’0’) then p_state

Electrical & Computer EngineeringMississippi State UniversityVHDL File for BlackJack Control (cont.)comb: process (p_state, ace11flag_pstate, broke_pstate, stand_pstate,acecard, card_rdy_dly, card_rdy_sync, score16gt, score21gt)beginsel

Electrical & Computer EngineeringMississippi State UniversityBlackjack Dealer Simulation (cont.)First card is an’Ace’.Next card isa ’2’Next card isa ’9’Final cardis a ’10’(facecard)Assertion ofSTAND fromprevious gamecauses us tostart newgame.We will use thefirst ’Ace’ as a valueof ’11’.Score = 11 + 2 = 1313 + 9 > 21 so we break;however, we have an ’Ace’so we can treat it as a valueof ’1’; the new score is:1 + 2 + 9 = 12.12 + 10 > 21 so weare ’BROKE’.Bob Reese 5/95System–31System Design with VHDL

Electrical & Computer EngineeringMississippi State UniversityStructural VHDL⇒ You do not have to use a schematic to connect VHDL blocks. Youcan write a structural VHDL model which ties the blocks together.⇒ Pros:→ When you synthesize the design all of the VHDL blocks areflattened (collapsed into one block) and it is possible that theresulting logic may be more efficient.→ The structural VHDL code is more portable to other designsystems than a schematic.⇒ Cons:→ Writing structural VHDL code can be more error prone thancreating a schematic (very easy to misplace a net when youdon’t have a ’picture’ to go by).→ The resulting flattened netlist can be more difficult to debug.Bob Reese 5/95System–32System Design with VHDL

Electrical & Computer EngineeringMississippi State UniversityStructural VHDL for BlackJack Playerentity bj_struct is port (Normal entitysignal reset_b, clk, card_rdy : in std_logic; declaration.signal card: in std_logic_vector(3 downto 0);signal stand, broke,hit:out std_logic;signal score: out std_logic_vector(4 downto 0) );end bj_struct;architecture structure of bj_struct iscomponent bjcontrol port (signal clk,reset_b:signal card_rdy, acecard:signal score16gt, score21gt:signal hit, broke,stand:in std_logic;in std_logic;in std_logic;out std_logic;signal sel: out std_logic_vector(1 downto 0);signal score_clear_b:out std_logic;signal score_load: out std_logic );end component;component bjdpathport (signal clk, reset_b:in std_logic;signal load, clear_b:in std_logic;signal sel: in std_logic_vector(1 downto 0);signal card: in std_logic_vector(3 downto 0);signal acecard, score16gt: out std_logic;signal score21gt:out std_logic;signal score: out std_logic_vector(4 downto 0) );end component;Need a component declarationfor each differenttype of componentused in the schematicBob Reese 5/95System–33System Design with VHDL

Electrical & Computer EngineeringMississippi State UniversityStructural VHDL for BlackJack Player (cont)signal load_net, clear_net, acecard_net : std_logic;signal sel_net : std_logic_vector (1 downto 0);signal s21gt_net, s16gt_net: std_logic;beginc1: bjcontrolport map (clk => clk,reset_b => reset_b,card_rdy => card_rdy,acecard => acecard_net,score16gt => s16gt_net,score21gt => s21gt_net,hit => hit, broke => broke, stand => stand,sel => sel_net,score_clear_b => clear_net,score_load => load_net);c2: bjdpathport map (clk => clk,reset_b => reset_b,load => load_net,clear_b => clear_net,sel => sel_net,card => card,acecard => acecard_net,score16gt => s16gt_net,score21gt => s21gt_net,score => score );end structure;Internal signal declarationfor those nets notconnected to externalports.Each component used in thedesign is given along withits port map.’c1’ is the component label,’bjcontrol’ gives the componenttype.Only two components inthis design.Bob Reese 5/95System–34System Design with VHDL

Electrical & Computer EngineeringMississippi State UniversityResults of bj_struct SynthesisBob Reese 5/95System–35System Design with VHDL