Logic Synthesis with VHDL System Synthesis Bob Reese Electrical ...

Electrical & Computer EngineeringMississippi State University1 2 3 4 5 6 7 81 2 3 4 5 6 7 8ABCDcinA1215411004119101210231214BCD652145621101281314897312151001961014814861411138151510151239845111373115732a(4)a(6)a(1)a(7)a(11)a(12)a(12)a(8)a(13)a(14)n1042813144893210a(15:0)a(15:0)n1044n1038n1031n1024n1018n1011n1027b(15:0)b(6)a(6)n1065n1016sum(6)0019236612756n1035b(7)b(11)n1043n1040n1041n1039n993 n1034sum(7)n1033a(7)n1037n1036b(7)7n1028n1029n1055 n1026sum(11)n1025a(11)n1030b(11)a(12)n1063b(12) n1022sum(12)n1023n1020b(15:0)n1021n1019n1057 n10131112n1015sum(13)n1012a(13)n1017b(13)n1060a(14)a(14) b(14) n1009b(14) n1062 n1010sum(14)n1061n1008n1007b(14)a(9) a(0) sum(0)n1005b(0)b(9)a(10)b(10)13140n997n958b(5)n1004sum(15:0)n1032n1053n994b(8)n984n1058n1059b(4)n1000a(10) sum(10)b(10)n1054 n976n974n1001n975b(0) n1056cin b(12) n973n965b(0)a(0)b(10)a(10)b(1) a(9)n966 sum(15)a(1) n1047n999b(1) n1048 n983b(2) n985a(2)b(12)n1014 a(1) sum(1)n991b(13)b(1)b(2) b(3)n967a(2) a(3)a(2)b(3) n988n968 b(2) sum(2)a(3)b(8)a(3) sum(3)n987b(8) b(3)a(8)n962a(5)n1006n1049n969 n996 sum(9)n964b(9) a(9)b(6) n1052n998b(5)n972n971a(6) n995a(8) n1064 sum(8)n961b(6) a(8)n977 n1002n980n981n979n970sum(4)a(4)n1046b(4)a(5)n1051n1003n1050n982sum(5)n1045n992n978n963n960n959n990n989n986b(15)n957a(15)a(15)b(15)coutsum(15:0)coutBob Reese 5/95System–12System Design with VHDL