Logic Synthesis with VHDL System Synthesis Bob Reese Electrical ...

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Electrical & Computer EngineeringMississippi State UniversityStructural VHDL⇒ You do not have to use a schematic to connect VHDL blocks. Youcan write a structural VHDL model which ties the blocks together.⇒ Pros:→ When you synthesize the design all of the VHDL blocks areflattened (collapsed into one block) and it is possible that theresulting logic may be more efficient.→ The structural VHDL code is more portable to other designsystems than a schematic.⇒ Cons:→ Writing structural VHDL code can be more error prone thancreating a schematic (very easy to misplace a net when youdon’t have a ’picture’ to go by).→ The resulting flattened netlist can be more difficult to debug.Bob Reese 5/95System–32System Design with VHDL
Electrical & Computer EngineeringMississippi State UniversityStructural VHDL for BlackJack Playerentity bj_struct is port (Normal entitysignal reset_b, clk, card_rdy : in std_logic; declaration.signal card: in std_logic_vector(3 downto 0);signal stand, broke,hit:out std_logic;signal score: out std_logic_vector(4 downto 0) );end bj_struct;architecture structure of bj_struct iscomponent bjcontrol port (signal clk,reset_b:signal card_rdy, acecard:signal score16gt, score21gt:signal hit, broke,stand:in std_logic;in std_logic;in std_logic;out std_logic;signal sel: out std_logic_vector(1 downto 0);signal score_clear_b:out std_logic;signal score_load: out std_logic );end component;component bjdpathport (signal clk, reset_b:in std_logic;signal load, clear_b:in std_logic;signal sel: in std_logic_vector(1 downto 0);signal card: in std_logic_vector(3 downto 0);signal acecard, score16gt: out std_logic;signal score21gt:out std_logic;signal score: out std_logic_vector(4 downto 0) );end component;Need a component declarationfor each differenttype of componentused in the schematicBob Reese 5/95System–33System Design with VHDL
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Logic Synthesis with VHDL System Synthesis Bob Reese Electrical ...

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