Logic Synthesis with VHDL System Synthesis Bob Reese Electrical ...
Logic Synthesis with VHDL System Synthesis Bob Reese Electrical ...
Logic Synthesis with VHDL System Synthesis Bob Reese Electrical ...
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<strong>Electrical</strong> & Computer EngineeringMississippi State UniversityBlackjack Dealer Simulation (cont.)First card is an’Ace’.Next card isa ’2’Next card isa ’9’Final cardis a ’10’(facecard)Assertion ofSTAND fromprevious gamecauses us tostart newgame.We will use thefirst ’Ace’ as a valueof ’11’.Score = 11 + 2 = 1313 + 9 > 21 so we break;however, we have an ’Ace’so we can treat it as a valueof ’1’; the new score is:1 + 2 + 9 = 12.12 + 10 > 21 so weare ’BROKE’.<strong>Bob</strong> <strong>Reese</strong> 5/95<strong>System</strong>–31<strong>System</strong> Design <strong>with</strong> <strong>VHDL</strong>
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