0 11 2 3 4 5 6-KEY:BUSTRAFFICB-CACHEMISS RATEw I-CACHE MISS RATEMEMORY IN GBFigure 4Normalized C,iclic Miss Rates and Rus Traffic0,5 0 L2 4 6 8KEY:H NORMALIZED Ipm AT 2 GB-- NORMALIZED lpm AT 8 GBNUMBER OF CPUsFigure 5CPU Scalins \.ct-si~s ~Vc~noryImproved CPU Scaling- More Efficient LockingA final hcncfit of using VLM is i~nprovcd symmetric~nulti~woccssi~ig (Sh4P) scaling. Rccausc the .1'1'( :-(:workload has seireral transactions \\*it11 high ~-e;ld content,lia\,ing thc data a\.ailable in mcmor!; rnthcr thanon disk, allo\\,s an SIMP system to perform morc efficicntly.~Morc requests call be scr\riccd that arc closer inc!,clcs to the (:PU. Data found in menlor\ is lcss thana microsecond a\\.a\., n.hereas cintn fo~~~lcl on disk ison the order of milliseconds n\\.a!..Wc lia\,c slio\\~~ ho\\ this sit~~ation impl-o\,cs tl~covcrall sytcm throughput. In addition, it i~np~-ovcsSIMP scaling. Figure 5 shows the rclnti\rc scalingbcnvccn 2 CPUs and 8 CPUs \\fit11 o~ily 2 GI< ofsystc~nmcmory (1.5 GK of database cache) cornpal-cd to thesame configurations having 8 GR of system memory(6.6 C;R ofclatabase cache).Wc used tlie performance countcrs on tllc Alpha2 1 164 ~nicroprocessor to monitor the nnmbcr ofcycles spent on thc rncmor!, barrier instr~~cltion."Mcmor!. bal.riers are required for i~nplcmcntingmutual cscl~~sion in the Alpha processor. T'lic\. arc uscclh!. all locking primitives in the dat.tbasc nnd the opcratingsystem. With VLhl at 8 GB of mcmor\r, \\.e nicasurcdn 20-percent decline in time spent ill the memorybarrier i~istruction. Larger nicmory implied lcss contcntionfor critical disk and 1/0 clinnncl rcso~~~.ccs andtl1~1s lcss time in thc memory barrier instruction.Conclusions01x11 systc~ii database vendors arc expanding intom;1infi3nic markets as open systcnis acquirc grckiterprocessing po\\.er, larger I/O subsystems, nnd thenbilit!? to deliver higher througl~pi~t at reasonablercs~onsc ti~ilcs. TO this end, Digitill's Alpli~Scr\.er8400 5/350 s!,stcrn using VT.M ciatnbnsc technolog!,I~as dc~nonstratcd substantial gains ill commercialperfvrlnancc \\die11 compared to systems \\'itlio~lt thecapability to use VtA4. Thc use ofup to 8 GI3 of mcmoryhelps increase system throughput by a factor of 2,e\Ien for dambascs that span 50 GR to 100 GK in size.The Digital AlpliaScr\,cr 8400 5/350 system combined\vith the 1)igital UNIS operating s!,stcm toaddress greater than 2 GR of n~cmory has made possibleimpro\.ed TP(:-(: results from several vendors. Inthis paper, \\,c lha\.c slio\\.n ho\\ VLhI1nc1.eascd the thro~lghput b!, a factor of nearl!. 2I~icrcascd the d.it;~basc-cnchc hit ratios fro111 88 percentto 95 pacentBy i~sing monitor tools designed for tlie Alpha platform,we 1ia\.c mcasurcd the effect of VLIM in issuingfewer instructions per tra~lsaction on the Alpha 21164microprocessor. When transactions are satisfied bydata that is alrcad!, in Incmor!; tlie CI'U has fe\\rerliard\\,are clachc misses, fc\\rcr mcmor!, barrier proccssorstalls, faster locking, anti bcttcr SMP scaling.Future Digitdl Alpl~aScr\.cr s!.srcms that \\.ill becapable of i~sing morc pl~!sical me~iiory nil1 bc able tohrther exploit V1.M database technolog. The resultsof industry-standard bcucli~narks such as TI'
Engineering Group); Marl< Davis and RJC~ Grove(C;ompilcrs Group); Peter Yalcutis (I/O PerformanceGroi~p); slid Don Harbert and Pa~~linc Nist (projectsl.x)~isors).References and Notes1. I). Fcn\\ficl
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IINTERNET PROTOCOL V.6DigitalTechni
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lie! elements of the protocol,Digit
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Intcrnct. Within tlic IETt', severa
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~~scd to store Iicccssar!z ciata an
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packets, \\,hilt the latter avoids
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* Test address for IPv4 characteris
- Page 16 and 17: ROUTER SOLICITATIONTYPECODECHECKSUF
- Page 18 and 19: 7 .ncn\.orlt. The solution is to al
- Page 20 and 21: AUTOCONFIGURATIONPROCESSINGUSER SPA
- Page 22 and 23: pilssing tlic olx~i x)ckcts to them
- Page 24 and 25: James P. BoundJIII~ Bol~nd 15 ,I co
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- Page 28 and 29: Table 2 (continued)Year Item Descri
- Page 30 and 31: Table 3Goals of the Australian Digi
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- Page 36 and 37: Table 8Architectures Implemented by
- Page 38 and 39: ucoder~ novaNOVA simulator V2.2bsim
- Page 40 and 41: BiographiesMaxwell M. BurnetMax Bur
- Page 42 and 43: no\\. tli;it appropriate stantlards
- Page 44: High Perfor~nance Fortran V1.l is c
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- Page 49 and 50: tllc s\,stcIn under test to use the
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- Page 53 and 54: III 8-CPU. 8-GB 8-CPU, 8-GB II -II
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- Page 61 and 62: TPC-C Benchmark7 -.I. lie TPC-C bcn
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- Page 71 and 72: Grc~pliical objccts such as definit
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- Page 77 and 78: Further ReadingsThc Digital Technic
- Page 79 and 80: J. Iroccssor," PI-ocec~di7rg.i ?/'l
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