Annual report 2009 - Imec

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IMEC CORE CMOS
HIgHLIgHTS - IC scaling today involves solving important challenges; the physical limits
of what is possible are nearing. Imec works to overcome these challenges, looking into
the use of new materials, new transistor types and new lithography techniques.
01
Source mask
optimization for 193nm
lithography
2009, imec started a project to look into source
mask optimization for the most advanced immersion
scanner available today, the ASML XT:1900i with a
numerical aperture of 1.35. A first such optimization
was with diffractive optical elements (DOE) to shape
the illumination source. Using DOEs, imec demonstrated
promising process window improvements on the
contact and metal1 layers of the 22nm SRAM layouts.
Imec also obtained first results with a flexible illuminator,
developed by ASML as an alternative to DOEs.
Such a flexible illuminator can shape any illumination
source in a computer-controlled way.
24
02
First 22nm SRAM
cell with
EUV lithography
2009, imec has fabricated the world’s first functioning
22nm CMOS SRAM cell. The 0.099µm² SRAM cells
have both the contact and metal1 layer printed using
EUV lithography. Compared to imec’s 32nm cell, the
area of the cells has been shrunk by 47%. For the frontend-of-line
process, imec used its high-k/metal-gate
FinFET platform. The front-end layers were printed
using immersion lithography.
03
Mask inspection
and cleaning for EUV
lithography
One of the obstacles for EUV lithography is that there
are no inspection tools for EUV masks. Currently the
most reliable way to inspect a mask is to illuminate a
batch of wafers and use these to look for repeating
defects, which will most probably originate from the
mask. As a shortcut to building new tools, we are studying
if existing inspection tools can be modified for
this purpose.