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arrier (Chapter 3), a durable templ<strong>at</strong>e surface tre<strong>at</strong>ment (Chapters 4 and 5), and a<br />

transfer layer th<strong>at</strong> adhered to the wafer and etch barrier while not swelling while in<br />

contact with the liquid etch barrier; (2) an imprint appar<strong>at</strong>us th<strong>at</strong> allowed consistent,<br />

hands-free oper<strong>at</strong>ion in order to remove much <strong>of</strong> the human component from the<br />

imprinting experiment (Chapter 7); and (3) a defect inspection tool th<strong>at</strong> would give<br />

an accur<strong>at</strong>e count <strong>of</strong> defects per imprint in a manner acceptable by the scientific<br />

community (Chapter 7).<br />

<strong>The</strong> end result <strong>of</strong> this work is a clear understanding <strong>of</strong> the fundamental<br />

process and equipment requirements for a defect study in imprint lithography, as<br />

well as a benchmark <strong>of</strong> defects over time using the SFIL process, which can be used<br />

as a launch pad for further process and equipment development.<br />

1.8 REFERENCES<br />

1. Scanlon, L., No P-N Intended, in Technology Review, 2003. 106(1): 88.<br />

2. Tristram, C., Supercomputing Resurrected, in Technology Review, 2003.<br />

106(1): 52-60.<br />

3. Moore, G., Proc. SPIE, 1995. 2438: p. 2-17.<br />

4. Intern<strong>at</strong>ional Technology Roadmap for Semiconductors. 1999,<br />

Semiconductor Industry Associ<strong>at</strong>ion: www.semichips.org.<br />

5. Thompson, L.F., C.G. Willson, and M.J. Bowden, Introduction to<br />

Microlithography. 2nd ed. 1994, Washington, D.C.: ACS.<br />

6. 3 rd Intern<strong>at</strong>ional SEMATECH Next Gener<strong>at</strong>ion Lithography Workshop.<br />

1999: Colorado.<br />

7. Associ<strong>at</strong>ion, S.I., Intern<strong>at</strong>ional Technology Roadmap for Semiconductors.<br />

2001: available <strong>at</strong> http://public.itrs.net/Files/2001ITRS/Home.html.<br />

17

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