lt tDrtrcnr or Eleiro.ics, Td@6o!!iolio, & ttior.di.rl E.linerttrg

CHAPTER 2
BACK GROUND AND LITERATLRE SURVEY
2.I OVERVIEW OF FPGA ARCHITECTURE
h gcne!{|. M l:lrcA consists ollogic blocks.l/O blocks, and progonhrbte rouling as
shown in liiSurc 2.1 To implenenr a circuit in m FPCA, each ofde losic blocks inrhe
n'c^ rc appop,idely posnnnEd b |).rtorfr
a smlll ponion o, rhc tlncrion.tny oa
rhe desircd cncun. and qch ollhe l/O blck is prognnmed lo h. an intut pad or an
ourprr l)jd $ rquned b! the cncun Thcn $csc fhclioml ponions a j I/Os are atl
aPtfotfurc, connecred ftoughrhcfhs nmiblc routins
Figure Ll: A g.n.ri. FPCA
1l