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DS 7-7R 17-12R Semiconductor Fabrication Facilities ... - FM Global

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7-<strong>7R</strong><br />

REFERENCE DOCUMENT<br />

<strong>17</strong>-<strong>12R</strong> SEMICONDUCTOR FABRICATION FACILITIES<br />

Page 20<br />

with the mask plate, and then exposed through the action of the shutter of the machine opening to allow ultraviolet<br />

light to hit the unmasked portion of the wafer.<br />

After the wafer has been aligned and exposed, the next step is developing. In developing a wafer, a machine<br />

similar to a ‘‘spinner’’ is used. The developing is done by chemicals which are sprayed down onto the wafer.<br />

This spray washes away the nonexposed resist (areas where the light was not allowed to pass through the<br />

mask plate) while the exposed or ‘‘polymerized’’ resist remains. The preferred developing chemical for negative<br />

photoresist is xylene. A Stoddard solvent may also be used in certain cases. Positive photoresist is developed<br />

in an alkaline solution, such as potassium hydroxide or sodium hydroxide.<br />

Other flammable solvents are also used in the wafer fabrication process. Butyl acetate and isopropyl alcohol<br />

will be used as washes for wafers after they have been developed with negative resist. D.I. water is more<br />

commonly used with positive photoresist as a post develop wash.<br />

Etching removes layers of silicon dioxide, metals and polysilicon as well as resists, according to desired<br />

patterns delineated by the resist. The two major categories of etching are wet and dry chemical. Wet etching<br />

is predominantly used and involves solutions containing the etchants (usually an acid mixture) at the<br />

desired strengths, which react with the materials to be removed. Plastic wet benches and plastic fume exhaust<br />

ductwork are typically used in wet etching operations (Figures <strong>17</strong> and 18 of Data Sheet 7-7/<strong>17</strong>-12). Dry etching<br />

involves the use of reactive gases (hydrogen chloride, ammonia, etc.) under vacuum in a highly energized<br />

chamber, which also removes the desired layers not protected by resist.<br />

To form the junctions where current will flow, a controlled number of impurities or dopants must be introduced<br />

into a selected region of the wafer either by diffusion or ion implantation. Diffusion is a high temperature<br />

(1652°F to 2372°F [900°C to 1300°C]) process in which certain chemicals (dopants) are introduced into<br />

the surface layer of the semiconductor material to change its electrical characteristics. Diffusion is the most<br />

established method of applying dopant material. Ion implantation is a technique for doping impurity atoms into<br />

an underlying substrate by accelerating the selected dopant ion towards the silicon target through an electrical<br />

field. Ion implantation is often preferred over standard diffusion methods because it is more precise,<br />

faster and less expensive. Annealing usually is required following ion implantation because of the structural<br />

damage caused by bombardment of the substrate by the accelerated ions.<br />

The need for annealing after ion implantation led to the development of a technology called Rapid Thermal<br />

Processing (RTP). This process, which takes place in seconds, eliminated the need for a minutes-long<br />

process in a tube furnace, which had undesirable side effects of migration of dopant atoms within the wafer.<br />

Also, every time a wafer is heated near diffusion temperatures and then cooled down, crystal dislocation<br />

forms, which can result in circuit failures. In the single wafer RTP tool, radiation heating (usually from tungsten<br />

halogen lamps) is very rapid and the body of the wafer never comes up to temperature. Annealing can<br />

take place without undesirable side effects. The trend to small feature sizes on wafers has also lead to thinner<br />

layers. Thermally grown gate oxide layers now may be less than 100 Angstroms thick. RTO ( Rapid Thermal<br />

Oxidation) tools are similar to the RTP annealing tools but have an oxygen atmosphere in the chamber<br />

rather than an inert gas. RTP technology is now used in various oxide, nitride and silicon layer processes.<br />

Deposition is the process of placing additional layers onto the wafer surface, either by epitaxial or chemical<br />

vapor deposition (CVD). Chemical vapor deposition is the process of forming a thin film on a substrate by<br />

the chemical reaction of various gases. CVD is usually promoted by heating the substrate, either at atmospheric<br />

pressure, or low pressure (LPCVD). Epitaxy is the process of depositing a crystalline layer having the<br />

same structure as the substrate. Epitaxy represents a special form of chemical vapor deposition. Often,<br />

epitaxial layers are grown with intentionally added impurities such as boron or phosphorus. These change<br />

the electrical conductivity of the crystalline silicon. Some of the more common process reactions can be found<br />

in Table 6 of Data Sheet 7-7/<strong>17</strong>-12.<br />

The photoresist, masking, etching, doping and deposition processes are repeated many times until the complete<br />

circuit is produced.<br />

After the final diffusion step, the devices which have been fabricated into the silicon wafer must be connected<br />

together to perform circuit functions. This process is known as metalization. Metalization provides a<br />

means of wiring or interconnecting the uppermost layers of integrated circuits by depositing complex patterns<br />

of conductive material, which route electrical energy within the circuits. To do this, a conductive metal is either<br />

sputtered or evaporated over the front of the wafer. A photoresist pattern is then aligned over the metal and<br />

some of it is etched away, leaving the desired metal coverage. The most common metals used for metalization<br />

are: aluminum, nickel, chromium, gold, copper, silver, titanium, tungsten and platinum.<br />

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