AVOIDING FURNACE SLIP IN THE ERA OF SHALLOW ... - MEMC

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apidly due to the extension of the sample. The graph in Fig. 8 shows that the silicon strength had been reduced to about 1/5 the original value after the dissolved oxygen concentration had been reduced from 30 ppma to 10 ppma (20 ppma precipitation). Upper Yield Stress at 800C (1E6 N/m 2 ) 60 50 40 30 20 10 0 Loss of Wafer Strength 0 5 10 15 20 25 Oxygen Precipitation (ppma79) Fig. 8: The loss of silicon wafer strength due to oxygen precipitation is shown by these tensile test results (23, 24). The experimental conditions are described in the text. For all wafers, the main strategy for avoiding furnace slip is to heat and cool the wafers in such a way that the center-to-edge temperature difference stays small enough that thermal stress due to nonuniform expansion is always less than the critical shear stress at the current wafer temperature. When the amount of oxygen precipitation is large (like that in the wafer shown in Fig. 4), then one must either make the furnace process extra gentle or reduce the amount of oxygen precipitation to avoid furnace slip. AVOIDING FURNACE SLIP IN WAFERS WITH SHALLOW TRENCH ISOLATION With the integration of shallow trench isolation (STI) into new IC fabrication processes, it became clear that the creation of dislocations during furnace processing had once again become a major problem (25). To produce STI structures, trenches are plasma etched into the silicon surface, the trenches are filled with CVD oxide, a densification anneal is done to fill gaps in the oxide (and to anneal out etch damage), and excess oxide is removed by CMP. Fig. 9 shows a typical cross section. Fig. 9: Sketch of STI cross section. After reference (26). Page 781
Since the thermal oxidation of silicon expands the volume by about 2.25, the subsequent thermal oxidation of the trench side walls expands the width of the oxide "D1" and puts the silicon into compression "C" and tension "T". The dashed lines in Fig. 9 separate the compressive and tensile regions and the black dots show the locations of maximum compression or tension (26). Several workers have discussed the stress the STI fill oxide exerts on the silicon. They have pointed out the benefits of minimizing the effects of oxide wedge growth (25-27), as well as minimizing the silicon stress by using a wider STI trench (26-27) or perhaps using a fill with voids (28). However, the contraction of the silicon wafer during furnace cooling has the same effect. As the wafer temperature decreases, the silicon contracts roughly 10 times as fast as the oxide (29). So in Fig. 9, the distance "D2" shrinks much faster than the distance "D1". At high temperatures, the oxide tends to flow and relieve the stress, but the oxide becomes two orders of magnitude more viscous for each 100C decrease in temperature (26). As the wafer cools toward the withdrawal temperature, the oxide becomes stiff while the wafer is still hot enough for dislocations to be created. If the wafer bows during cooling so that the front side is concave, the compressive stress of bowing would add to the existing stresses. Bowing could explain the spot of high diode leakage in the center of the wafer of reference (28). Figure 10 shows typical STI dislocations. Fig. 10: SEM photos of STI structures after fab processing, HF strip-back, and a brief Schimmel etch. The LEFT photo shows a dislocation threading from the bottom corner of one trench to the bottom corner of the adjacent trench. The RIGHT photo shows a dislocation threading through the silicon pillar. A series of furnace slip experiments was done over a time that included two generations of STI-technology devices. Figure 5 shows an x-ray topography image for a 200mm wafer with STI structures which had been through an 1150C oxide densification anneal with ramp rates similar to those shown in Table I. Dislocations were present along edge slip lines at the front surface of the wafer, affecting an area of 20 cm 2 . A companion wafer without STI structures showed no dislocations at the front surface. The slip evident in Fig. 5 was initiated at spots of contact damage on the wafer back side. Some of this damage occurred due to contact with the vertical furnace boat slots during the densification anneal and some occurred during prior processing steps. Figure 11 shows a backside damage spot after the anneal. Figure 11 shows local slip with dislocations punched out in directions along the surface. X-ray topography also showed dislocations punched out in the directions below the surface toward the front surface of the wafer. Page 782
Page 1 and 2: In Semiconductor Silicon 2002, H.R.
Page 3 and 4: during furnace slip are lines of si
Page 5 and 6: When a boat of wafers is inserted i
Page 7: at 800C, the insertion/withdrawal r
Page 11 and 12: CONCLUSION During furnace processin

AVOIDING FURNACE SLIP IN THE ERA OF SHALLOW ... - MEMC

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