AVOIDING FURNACE SLIP IN THE ERA OF SHALLOW ... - MEMC
AVOIDING FURNACE SLIP IN THE ERA OF SHALLOW ... - MEMC
AVOIDING FURNACE SLIP IN THE ERA OF SHALLOW ... - MEMC
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In Semiconductor Silicon 2002, H.R. Huff, L. Fabry, and S. Kishino, Editors, PV 2002-2, p. 774, The Electrochemical<br />
Society Proceedings Series, Pennington, NJ (2002).<br />
<strong>AVOID<strong>IN</strong>G</strong> <strong>FURNACE</strong> <strong>SLIP</strong> <strong>IN</strong> <strong>THE</strong> <strong>ERA</strong> <strong>OF</strong><br />
<strong>SHALLOW</strong> TRENCH ISOLATION<br />
Anthony E. Stephens<br />
<strong>MEMC</strong> Electronic Materials<br />
Silicon Engineering Technology Center<br />
P.O. Box 9600, Sherman, Texas 75091-9600, USA<br />
Although the silicon wafer is strong at room temperature, it is weak at<br />
the elevated temperatures necessary for the fabrication of integrated<br />
circuits. During thermal processing, a nonuniform elevated temperature<br />
produces a nonuniform expansion within the wafer and the resulting lattice<br />
forces can cause local or widespread furnace slip. This disrupts the silicon<br />
crystal structure and permanently degrades the electrical and physical<br />
characteristics of the wafer. Matters are made worse when shallow trench<br />
isolation structures are built into the wafer surface. During thermal<br />
cycling, the pressure oxide exerts on the silicon side-walls can create<br />
dislocations or cause slip-dislocations to move into the device.<br />
The causes of furnace slip are examined, and the effects on integrated<br />
circuit yield and reliability are reviewed. Characterization methods and<br />
the characteristic wafer failure modes are described. The factors that<br />
influence the wafer’s resistance to furnace slip and the appropriate<br />
corrective actions are discussed. A case study is used to describe how<br />
shallow trench isolation structures and processing exacerbate the problem<br />
of furnace slip.<br />
<strong>IN</strong>TRODUCTION<br />
Decades of fabricating integrated circuits on silicon wafers have shown that furnace<br />
slip is always a problem. This is because the fabrication engineer is always faced with<br />
the conflicting goals of increasing the speed of furnace temperature ramps and push-pull<br />
steps to maximize the furnace throughput, while at the same time limiting the speed of<br />
temperature ramps and push-pull steps to prevent wafer warpage and the creation of<br />
yield-killing slip dislocations. Each time the wafer diameter increased, a new balance<br />
had to be found. Then, with the introduction of oxide-filled shallow trench isolation<br />
(STI) structures, furnace recipes which had produced slip-free wafers previously became<br />
recipes which produced massive furnace slip. In this paper we discuss actions that are<br />
necessary to re-establish the balance between maximizing furnace throughput and<br />
preventing dislocation creation in order to successfully fabricate integrated circuits with<br />
STI structures.<br />
We discuss in turn the basics of furnace slip, integrated circuit (IC) failure modes,<br />
wafer characterization methods, wafer failure modes, and actions directed toward<br />
Page 774
educing furnace slip. Then we use a case study to discuss the additional actions<br />
necessary to successfully process wafers with STI structures.<br />
<strong>FURNACE</strong> <strong>SLIP</strong><br />
At room temperature, the single-crystal silicon wafer is elastic and brittle. If a small<br />
mechanical stress such as a bending stress is applied, the wafer is temporarily deformed.<br />
When the small stress is removed, the wafer returns to its original shape with its crystal<br />
structure unchanged. But if an excessively large stress is applied to a wafer at room<br />
temperature, it will fail due to brittle fracture.<br />
During furnace processing at temperatures above about 750C (1), the wafer is elastic<br />
and plastic. If a small mechanical stress is applied and then removed, the wafer will<br />
deform and then return to its original shape with the crystal structure undamaged. But if<br />
an excessively large stress is applied at an elevated temperature, the wafer will fail due to<br />
plastic deformation (furnace slip). The furnace slip changes the shape of the wafer and<br />
produces slip-dislocations (2-5).<br />
During the thermal processing steps that are necessary for fabricating IC devices, the<br />
wafer is subjected to numerous mechanical stresses. Stresses occur during heat-up and<br />
cool-down because dissimilar materials used for IC construction expand and contract at<br />
different rates. If not properly constructed, the boat or fixture used to hold the wafer<br />
during thermal cycling can exert mechanical stresses on the wafer. If, during heat-up,<br />
during annealing, or during cool-down, one part of the wafer is at a different temperature<br />
than another part of the wafer, then the wafer is being subjected to internal mechanical<br />
stresses due to nonuniform silicon expansion. The furnace slip that can occur in the<br />
wafer due to a nonuniform temperature distribution will be described in some detail<br />
below.<br />
A nonuniform temperature distribution may or may not produce furnace slip. Slip is<br />
more likely if the temperature is higher, if the temperature spatial gradient is higher, if the<br />
amount of oxygen precipitation is higher, and if there are more surface or imbedded IC<br />
features which create and concentrate the stress. Since the silicon becomes softer or<br />
weaker with increasing temperature, the local temperature is an important factor in<br />
determining where in the wafer the slip takes place. Slip begins with a shearing of the<br />
layer of single covalent bonds between silicon atoms in adjacent {111} planes. As the<br />
{111} planes slip with respect to each other, dislocations are created. Although the<br />
change in wafer shape relieves some of the stresses caused by the nonuniform<br />
temperature and expansion, the wafer will be deformed and new elastic stresses will be<br />
present when the wafer returns to room temperature.<br />
Furnace slip reduces IC fabrication yield and in some cases creates reliability<br />
problems. If the wafer is warped or bowed too severely, it may not be possible to pull it<br />
down on a vacuum chuck for subsequent lithography steps. If there is only local<br />
deformation, pulling the wafer down on a vacuum chuck may cause the distorted part of<br />
the wafer to be shifted laterally so the patterns on that part of the wafer are misaligned<br />
with respect to the patterns elsewhere on the wafer. The dislocations that are produced<br />
Page 775
during furnace slip are lines of silicon atoms that have no adjacent silicon atom to bond<br />
to. Dislocations can serve as dopant diffusion pipes, so that IC junctions are not smooth<br />
but spiked. Dislocations getter metallic impurity atoms and become highly conductive<br />
paths. Dislocations with gettered metal atoms are effective generation and recombination<br />
sites. Dislocations across junctions cause reverse bias junction leakage and increased IC<br />
power consumption. Dislocations at storage capacitors can cause loss of stored DRAM<br />
charge and pause refresh failure.<br />
Several methods are available for characterizing furnace slip. The plot of a wafer’s<br />
freestanding warp can be used to detect and diagnose large-scale slip. A warp plot is a<br />
topographic map or a projected drawing that shows the shape of the wafer when it is not<br />
clamped or pulled down on a vacuum chuck. Examples of warp plots are shown in Figs.<br />
1 and 2.<br />
Fig. 1: Freestanding warp plots of a {100} wafer that suffered severe furnace slip during<br />
insertion into a furnace tube. The height contour lines show 2 µm intervals.<br />
Fig. 2: Freestanding warp plots of a {100} wafer that suffered severe furnace slip during<br />
withdrawal from a furnace tube. The height contour lines show 2 µm intervals.<br />
An interference contrast microscope can be used to view slip steps on the wafer surface<br />
or to view the dislocation etch pits produced by a defect etch. Figure 3 shows slip steps<br />
and dislocation etch pits on the upper {100} surface of a wafer. Figure 4 shows<br />
dislocation etch pits on the cleaved and etched {110} surface of a wafer.<br />
Page 776
Fig. 3: The LEFT photo shows slip steps at the edge of a P{100} wafer as revealed by an<br />
interference contrast microscope. The RIGHT photo shows dislocation etch pits at a P{100}<br />
wafer surface after HF strip-back and 3 min Schimmel etch (6).<br />
Fig. 4: The photo shows rows of diamond-shaped dislocation etch pits at the cleaved {110}<br />
surface in the center of a P/P+{100} epi wafer. The cleaved surface was etched for 3 min in<br />
Leo’s etch (7). Many large oxygen precipitation defects are also observed in the P+.<br />
Other slip characterization methods include Makyoh (magic mirror) topography (8),<br />
minority carrier recombination lifetime mapping (9), and scanning Lang transmission xray<br />
topography (10-12). Figure 5 shows an x-ray topography image.<br />
Fig. 5: X-ray topography image of one edge of an in-process P{100} wafer after HF stripback<br />
and 3 min Schimmel etch. The black spots are damage sites on the back side of the<br />
wafer and the many dark lines are dislocations in the wafer bulk.<br />
Page 777
When a boat of wafers is inserted into a tube furnace, furnace slip can occur as<br />
follows. The wafers are closely spaced in the furnace boat, and their initial temperature<br />
is low and uniform. As the wafers move into the furnace tube, radiation from the furnace<br />
tube heats up the outer edges of the wafers. Each wafer shadows the centers of the<br />
adjacent wafers, so the wafer centers heat up more slowly than the edges. A similar<br />
situation exists when the temperature of the furnace tube is ramped upward. The uneven<br />
heating causes the temperature of the outer edge of each wafer to increase faster than the<br />
temperature of the wafer center. The silicon around the wafer edge expands and softens<br />
as the local temperature rises, but the silicon in the center of the wafer expands less and<br />
remains stronger because of the slower rise in temperature there. If the stresses<br />
developed by the nonuniform expansion become large enough, then silicon-to-silicon<br />
bonds are sheared and the stresses are partially relieved by slip between individual {111}<br />
planes in the softened outer edge of the wafer. In the more severe cases, the silicon slips<br />
on many {111} planes and the net result is a bending of the softened silicon near the<br />
wafer edge to accommodate the increased wafer circumference. This plastic deformation<br />
creates many dislocations in localized regions near the wafer edge and causes the entire<br />
wafer to be warped.<br />
Figure 1 shows the typical shape of a wafer that has suffered severe furnace slip<br />
during a furnace insertion or temperature ramp-up. The shape can be described as that of<br />
a saddle, with two opposite edges turned up and the other two edges turned<br />
down. Sometimes the wafer appears to be folded along one of the two directions.<br />
The highest densities of dislocations are found at the locations where the local curvature<br />
is highest and are found at the surface which is locally concave (13).<br />
When a boat of wafers is withdrawn from a tube furnace or the tube temperature is<br />
ramped downward, furnace slip can occur as follows. The wafers are closely spaced in<br />
the furnace boat and their initial temperature is high and uniform. As the wafer<br />
environment is cooled, each wafer radiates energy from the edge and the temperature of<br />
the wafer edge decreases faster than the temperature of the wafer center. The silicon<br />
around the wafer edge shrinks and gets stronger as the temperature decreases, but the<br />
silicon in the center of the wafer shrinks more slowly and remains softer due to the<br />
slower decrease in the temperature there. The shrinking silicon around the wafer edge<br />
squeezes the wafer center and increases any preexisting wafer bow. If the compressive<br />
thermal stresses are great enough, then the stresses are partially relieved as inverted<br />
pyramids of silicon (bounded by {111} planes) slip toward the wafer surface in the center<br />
of the wafer on the concave side (3, 14, 15). In the more severe cases, plastic<br />
deformation in the wafer center leads to high dislocation densities and severe permanent<br />
bow.<br />
Figure 2 shows the typical shape of a wafer that has suffered severe center slip<br />
during a furnace withdrawal or a temperature ramp-down. The wafer is permanently<br />
bowed. A high density of dislocations is found in the central region of the wafer and a<br />
low density of dislocations is found at the wafer edge. As reported by Leroy and<br />
Plougonven (3), the dislocations in the center of the wafer are found near the concave<br />
surface. This is illustrated in Fig. 4. The wafer in Fig. 4 was bowed so that the front<br />
surface was concave. During cooling, the shrinking periphery increased the amount of<br />
Page 778
ow, putting the front surface into strong compression and causing slip to take place<br />
there.<br />
The IC failure pattern can sometimes provide a clue that furnace slip has taken place.<br />
Figure 6 shows a case where too-rapid heating created slip-dislocations at the wafer<br />
edges and a case where too-rapid cooling created dislocations in the wafer center on the<br />
concave side.<br />
Fig. 6: IC leakage failure patterns due to furnace slip. The leakage fail pattern on the<br />
LEFT was caused by dislocations created by rapid edge-first heating of a P{100} wafer. In<br />
this case the wafer was not highly warped, but slip-dislocations were concentrated at the<br />
four edges. The black-dot leakage fail pattern on the RIGHT was caused by rapid<br />
edge-first cooling of the P/P+{100} wafer shown in Fig. 4.<br />
<strong>AVOID<strong>IN</strong>G</strong> <strong>FURNACE</strong> <strong>SLIP</strong><br />
Furnace slip can be avoided, or at least reduced to a tolerable level, by reducing the<br />
nonuniform expansion and contraction within the wafer and by managing the stresses<br />
caused by nonuniform expansion and contraction. Factors which affect the silicon<br />
wafer’s strength and the associated corrective actions are discussed in this section. Issues<br />
related to STI structures and dissimilar materials are discussed in the next section.<br />
Slip begins when the component of stress that is directed along a {111} plane<br />
exceeds the critical stress that is required to shear the silicon-to-silicon bonds between<br />
{111} planes. This critical shear stress decreases with increasing temperature, so the<br />
wafer becomes weaker or softer as the temperature increases.<br />
A sense of how the wafer becomes more susceptible to furnace slip as the<br />
temperature is increased from 700C to 950C is shown in Fig. 7. In this simple<br />
experiment (16), bare 150mm P{100} wafers were placed on a fixture which supported<br />
the wafers around the edge. Each wafer was heated to a given temperature and then<br />
subjected to a bowing stress for 1 min by applying a vacuum to the bottom side of the<br />
wafer so that the air pressure was 240 torr higher on the top side of the wafer than on the<br />
bottom. Depending on the temperature of the wafer, this caused some amount of center<br />
slip and plastic deformation. After cooling, the amount of permanent bow was measured.<br />
Figure 1 shows why slip is much more likely to occur during an 800C furnace insertion<br />
or withdrawal as compared to a 750C insertion or withdrawal. When the furnace tube is<br />
Page 779
at 800C, the insertion/withdrawal rate must be made quite low to prevent the center-toedge<br />
temperature difference in the wafer from becoming so large that slip takes place.<br />
Bow (mm)<br />
10<br />
8<br />
6<br />
4<br />
2<br />
0<br />
Permanent Bow after 1 min Stress<br />
700 750 800 850 900 950<br />
Temperature (C)<br />
Fig. 7: This graph shows the loss of wafer strength as the temperature is increased (16).<br />
The experimental conditions are described in the text.<br />
The wafers become progressively weaker as the temperature is increased to higher<br />
values, and the furnace temperature ramp-up and ramp-down rates must be progressively<br />
reduced to prevent slip. Table I gives ramp rates that have given slip-free results for<br />
200mm wafers in a variety of wafer fab processes, but without shallow trench isolation.<br />
Table I. Acceptable Furnace Ramp Rates for an 1150C Anneal of 200mm Wafers.<br />
Temperature Ramp-Up Temperature Ramp-Down<br />
Range Rate<br />
Range Rate<br />
750C - 1000C 7 C/min 1150C - 1100C 2 C/min<br />
1000C - 1100C 3 C/min 1100C - 1000C 3 C/min<br />
1100C - 1150C 2 C/min 1000C - 750C 3 C/min*<br />
The value marked * could be 7 C/min if the furnace has fast-ramp capability. For<br />
temperatures near 1200C, a 1 C/min ramp rate is generally necessary. The values in<br />
Table I are for a 4.75 mm wafer-to-wafer spacing in the furnace boat. One can use a<br />
wider wafer spacing in order to reduce the center-to-edge temperature difference and the<br />
stress. Nilson and Griffiths have developed analytical models of furnace processing (17)<br />
and given a relation for calculating the wafer center-to-edge temperature difference<br />
during furnace temperature ramping (18). This relation can be used to calculate the<br />
influence of wafer spacing and wafer dimensional factors.<br />
Dissolved oxygen strengthens the wafer by pinning dislocations (19-22). However,<br />
oxygen precipitation weakens the wafer by depleting the dissolved oxygen and by<br />
punching out additional dislocations at the growing oxygen precipitates. The weakening<br />
effect of oxygen precipitation is shown in Fig. 8 (23). In this experiment, wafers with an<br />
initial dissolved oxygen concentration of 30 ppma (24) were annealed for various times at<br />
1050C to induce oxygen precipitation. Dog-bone shaped tensile test samples were cut<br />
from the wafers and subjected to tensile testing at 800C in order to measure the upper<br />
yield stress. The upper yield stress is the stress at which dislocations begin to multiply<br />
Page 780
apidly due to the extension of the sample. The graph in Fig. 8 shows that the silicon<br />
strength had been reduced to about 1/5 the original value after the dissolved oxygen<br />
concentration had been reduced from 30 ppma to 10 ppma (20 ppma precipitation).<br />
Upper Yield Stress at 800C<br />
(1E6 N/m 2 )<br />
60<br />
50<br />
40<br />
30<br />
20<br />
10<br />
0<br />
Loss of Wafer Strength<br />
0 5 10 15 20 25<br />
Oxygen Precipitation (ppma79)<br />
Fig. 8: The loss of silicon wafer strength due to oxygen precipitation is shown by these<br />
tensile test results (23, 24). The experimental conditions are described in the text.<br />
For all wafers, the main strategy for avoiding furnace slip is to heat and cool the<br />
wafers in such a way that the center-to-edge temperature difference stays small enough<br />
that thermal stress due to nonuniform expansion is always less than the critical shear<br />
stress at the current wafer temperature. When the amount of oxygen precipitation is large<br />
(like that in the wafer shown in Fig. 4), then one must either make the furnace process<br />
extra gentle or reduce the amount of oxygen precipitation to avoid furnace slip.<br />
<strong>AVOID<strong>IN</strong>G</strong> <strong>FURNACE</strong> <strong>SLIP</strong> <strong>IN</strong> WAFERS WITH <strong>SHALLOW</strong> TRENCH ISOLATION<br />
With the integration of shallow trench isolation (STI) into new IC fabrication<br />
processes, it became clear that the creation of dislocations during furnace processing had<br />
once again become a major problem (25). To produce STI structures, trenches are<br />
plasma etched into the silicon surface, the trenches are filled with CVD oxide, a<br />
densification anneal is done to fill gaps in the oxide (and to anneal out etch damage), and<br />
excess oxide is removed by CMP. Fig. 9 shows a typical cross section.<br />
Fig. 9: Sketch of STI cross section. After reference (26).<br />
Page 781
Since the thermal oxidation of silicon expands the volume by about 2.25, the<br />
subsequent thermal oxidation of the trench side walls expands the width of the oxide<br />
"D1" and puts the silicon into compression "C" and tension "T". The dashed lines in Fig.<br />
9 separate the compressive and tensile regions and the black dots show the locations of<br />
maximum compression or tension (26). Several workers have discussed the stress the<br />
STI fill oxide exerts on the silicon. They have pointed out the benefits of minimizing the<br />
effects of oxide wedge growth (25-27), as well as minimizing the silicon stress by using a<br />
wider STI trench (26-27) or perhaps using a fill with voids (28).<br />
However, the contraction of the silicon wafer during furnace cooling has the same<br />
effect. As the wafer temperature decreases, the silicon contracts roughly 10 times as fast<br />
as the oxide (29). So in Fig. 9, the distance "D2" shrinks much faster than the distance<br />
"D1". At high temperatures, the oxide tends to flow and relieve the stress, but the oxide<br />
becomes two orders of magnitude more viscous for each 100C decrease in temperature<br />
(26). As the wafer cools toward the withdrawal temperature, the oxide becomes stiff<br />
while the wafer is still hot enough for dislocations to be created. If the wafer bows<br />
during cooling so that the front side is concave, the compressive stress of bowing would<br />
add to the existing stresses. Bowing could explain the spot of high diode leakage in the<br />
center of the wafer of reference (28).<br />
Figure 10 shows typical STI dislocations.<br />
Fig. 10: SEM photos of STI structures after fab processing, HF strip-back, and a brief<br />
Schimmel etch. The LEFT photo shows a dislocation threading from the bottom corner of<br />
one trench to the bottom corner of the adjacent trench. The RIGHT photo shows a<br />
dislocation threading through the silicon pillar.<br />
A series of furnace slip experiments was done over a time that included two<br />
generations of STI-technology devices. Figure 5 shows an x-ray topography image for a<br />
200mm wafer with STI structures which had been through an 1150C oxide densification<br />
anneal with ramp rates similar to those shown in Table I. Dislocations were present<br />
along edge slip lines at the front surface of the wafer, affecting an area of 20 cm 2 . A<br />
companion wafer without STI structures showed no dislocations at the front surface. The<br />
slip evident in Fig. 5 was initiated at spots of contact damage on the wafer back side.<br />
Some of this damage occurred due to contact with the vertical furnace boat slots during<br />
the densification anneal and some occurred during prior processing steps. Figure 11<br />
shows a backside damage spot after the anneal. Figure 11 shows local slip with<br />
dislocations punched out in directions along the surface. X-ray topography also<br />
showed dislocations punched out in the directions below the surface toward the<br />
front surface of the wafer.<br />
Page 782
Figure 12 shows dislocations associated with laser scribe marks. In this case, many<br />
dislocations were observed in the STI region away from the scribe marks, but few were<br />
observed immediately adjacent to the scribe marks where no STI structures were present.<br />
Fig. 11: The photo shows punched-out<br />
dislocations around a backside contact<br />
damage spot after STI anneal, strip-back<br />
and 5 min Schimmel etch.<br />
Page 783<br />
Fig. 12. The x-ray topography image shows<br />
dislocations associated with, but not<br />
immediately adjacent to, the laser scribe<br />
marks.<br />
In these experiments, dislocations at the front surface of the wafer were found along<br />
slip lines near the wafer edges, but not in the central region. In many cases, the<br />
dislocation etch pits were tear-drop shaped and arranged as closely spaced pairs along a<br />
slip line. These were evidently short, shallow dislocation loops lying between the {111}<br />
planes where the wafer had slipped. During furnace temperature ramp-up, the edge-first<br />
heating causes the wafer to experience a compressive hoop stress around the edge. This<br />
compressive hoop stress may have combined with the localized stress within the STI<br />
structures to create local dislocation loops. Alternatively, the local STI stress may have<br />
trapped pinched-off sections of a slip-dislocation. Whatever the sequence of events,<br />
dislocations within the device are detrimental.<br />
Based on the series of STI furnace slip experiments, the following advice can be<br />
offered for fabricating devices with STI:<br />
1) The furnace ramp rates for 200mm wafers must be somewhat slower than those<br />
shown in Table I. (The ramp rates near the maximum temperature were the most<br />
important.)<br />
2) The oxide densification anneal should be done at a relatively low temperature.<br />
(Reducing the anneal temperature from 1150C to 1050C to 1000C gave less slip.)<br />
3) The technology and tool for doing the CVD oxide deposition should be carefully<br />
chosen based on experiment. (Slip varied widely from TEOS deposition tool to tool. A<br />
high density plasma tool worked well.)<br />
4) The insertion/withdrawal temperature should be low. (After other factors were<br />
optimized, 650C gave slightly better results than 750C.)<br />
5) Re-optimize for each new (smaller) version of the STI-containing device. (If the<br />
STI trench becomes narrower, the oxide will be less compressible.)
CONCLUSION<br />
During furnace processing, a nonuniform elevated temperature produces a<br />
nonuniform expansion within the wafer and the resulting lattice stress can cause local or<br />
widespread furnace slip. This problem is made worse when shallow trench isolation<br />
structures are built into the wafer surface. After oxidation and during thermal cycling,<br />
the stress the isolation oxide exerts on the silicon, plus the stress caused by nonuniform<br />
wafer expansion can create dislocations or cause slip-dislocations to move into the<br />
leakage-sensitive parts of the IC device. But by moderating both the furnace stress and<br />
the internal stress, IC devices with STI structures can be fabricated successfully.<br />
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Page 784
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