The Signetics 2650 - The MESSUI Place

tends to introduce hassles when you try
to use certain 5-100 boards. The choice
is up to you.
Of course, some of the 5-100 control
signals are more important than others.
Some signals are only needed if you
plan to have a fancy front panel on your
system — a feature which is not as popular
nowadays as it was. Others are only
used for things like a hardwareimplemented
single step facility, or
stack management hardware external
to the processor. If you don't want
these facilities, or don't need them,
then the signals can be ignored.
Perhaps the remaining general point
that should be made about the S-100
bus is that as you can see, it uses two 8bit
data buses: one for data into the
processor, and the other for data out of
the processor. This is a carryover from
the original Altair design, and is again a
little clumsy by modern standards. In
general only one of the two buses is
ever in use at any instant, so it would be
more elegant and efficient to have a
single bidirectional bus.
But if you want to make your interface
compatible with most of the 5-100
plug-ins, you have to provide for the
two separate data buses — clumsy
though they may be. Of course you can
always provide your own bidirectional
bus as well, using eight of the unstandardised
pins. Just make sure that the
pins you use aren't needed by any of
your S-100 plug-ins for special control
signals.
Well then, let's get down to specifics.
What's involved in providing an 5-100
interface for your 2650 Mini Computer
system?
Before going any further, I would like
to stress that the remainder of this article
consists basically of a set of
suggestions, rather than the description
of an interface that has been built up
and tested. The circuit diagram given
has not been tested, as this would have
involved a considerable amount of time
and effort which could not really be
justified in view of the limited interest.
But it has been prepared from a careful
survey of 5-100 literature and reference
material, and I believe it to be fully
practical.
Basically if you want to provide your
2650 system with an S-100 interface
which provides each and every one of
the various standardised control
signals, it isn't easy. But on the other
hand, some of the control signals turn
out to be unnecessary in a 2650-based
system, except in very rare circumstances.
The interface shown in the circuit
diagram provides only the main control
signals, but should be suitable for interfacing
your 2650 system to most S-100
plug-ins.
Let's run through the circuit, starting
from the bottom and working upward.
First are the 16 address lines ADO-AD15,
buffered by a pair of 81L595 or similar
Tri-state octal buffers. The inputs for
48 SINP Status output Signal which, when high, Indfcates that the address bus
Contains the address of an Input device and the Input date should be
placed on the data bus when PDBIN Is active.
47 SMEMR Memory Read — Status output signal which, when high. Indicates
that the data bus will be used to read memory data.
48 SHLTA Halt Acknowledge — Status output signal which, when high,
acknowledges that a HALT instruction has been executed.
49 ILO Phase 2 clock inverted
50 GND Signal end power grOund
51 +8V Same as pin 1
52 =16‘.! Negative unregulated voltage supply
53 SSW DSB Sense Switch Disable — A low disables the data input buffers so the
Input from the sense switches may be strobed onto the bidirectional
data bus.
54 EXT CLR External Clear — A low clears I/O devices.
55
56
57
58
59
60
61
These pins not standardised.
62
63
64
65
66
67
68 MWRITE Memory Write — A high indicates that the current data on the Date
Out Bus Is to be written into the memory location currently on the ad-
dress bus.
69 Status of protect flpflop (low for protect).
70 PROT Protect — A positive pulse sets the protect filpflop.
71 RUN Run — A high indicates that the Run/Stop filpflop Is set to RUN.
72 eaa Ready — See pin 3.
73 PINT Interrupt Request.— A low causes the processor to recognise en in-
terrupt request at the end of the current Instruction or while halted. If
the CPU Is In the Hold state or if the Interrupt Enable MAIN) is reset.
It will not honour the request.
74 PF=1 Hold — A low requests the processor to enter the Hold state. It allows
an external device to gain control of the address end data buses as
soon as the current machine cycle is completed.
75 PRESET Reset — A low causes the contents of the program counter to be
cleared and the instruction register is Set to 0.
78 PSVNC Sync — The command/control signal out which, when high, Identifies
the beginning of an 8080 machine cycle.
77 PWR Write -7 the command/control signal out which, when low, signifies
the presence of valid date on the Data Out bus.
78 PDBIN Data Bus in — The commend/control signal out which, when high.
requests data on the DI bus from the addressed memory or I/O.
79 AO Address Bit 0
80 Al Address Bit .l
81 A2 Address Bit 2
82 AS Address Bit 6
83 A7 Address Bit 7
84 A8 Address Bit 8
85 A13 Address Bit 13
86 A14 Address Bit14
87 All Address Bit 11
88 DO2 Data Out Bit 2
B9 DO3 Data Out Bit 3
90 007 Data Out Bit 7
91 014 Data In Bit 4
92 015 Data in Bit 5
93 D16 Data in Bit 8
94 Dil Data in Bit 1
95 DIO Date In Bit 0
96 SINTA Interrupt Acknowledge — The status output signal which, when high,
Identifies the instruction fetch owlets) that Immediately follow en
accepted Interrupt request presented on Wt.
97 SWO Write/Output — The statue output signal Identifying a bus cycle
which. when low, transfers data from processor to memory or I/O.
98 SSTACK Stack — Status output signal which indicates, when high, that the ad-
dress bus holds the pushdown stack eddress from the Steck Pointer
and that a stack operation will occur on the current cycle.
99 POC Power On Clear — Generated by PRESET or power on. Used to reset
CPU and I/O devices.
100 GND Signet and power ground
ELECTRONICS Australia, January, 1980 83