The Signetics 2650 - The MESSUI Place

84 ELECTRONICS Australia, January, 1980
the buffers are taken from the address
lines (already buffered) on the 2650
Mini Computer's expansion board. —
Note that the S-100 bus requires 16
address lines, whereas the 2650 system
only has 15 lines available (ADO-AD14).
The input of the 16th buffer is therefore
tied permanently to ground.
One enable input of each of the
811595 address buffer devices is connected
to a gate. This allows the buffers
to be disabled, and the 5-100 address
lines to be floated in a high Impedance
state, either in response to the
ADD DSB-bar signal (pin 22) or when
the processor is halted. Other 5-100
boards are thus able to take control of
the address lines, for things like DMA
(direct memory access) data transfers.
Moving upward, we find two more
81L595 octal buffers, the first used to
buffer the 5-100 data out lines 000-
D07, and the second to buffer the 5-
100 data input lines DIO-D17. As with
the address buffers, the data out buffers
are controlled by another gate, so they
can be disabled either in response to
the DO DSB-bar signal (pin 23) or when
the processor is halted.
In addition, both the DO and DI
buffers are controlled separately by two
of the outputs of an 825103 device. This
is a programmable gate array, which
Signetics and Philips are making
available pre-programmed with the
logic functions necessary to generate
eight key 5-100 control signals from the
existing 2650 control signals OPREQ, Rbar/W,
M/I0-bar and WRP.
As you can see, besides the two data
buffer control signals the device also
produces the S-100 signals SOOT (pin
45), SINP (pin 46), SMEMR (pin 47),
PWR-bar (pin 77), PDBIN (pin 78) and
MWRT (pin 68). So it really takes some
of the hassles out of making the 2650
"pretend" to be an 8080!
The preprogrammed version of the
825103 is coded with the suffix CK1179,
and is available from your normal parts
supplier on order from Philips Industries.
It should cost you less than
$10, including tax.
The programming chart for the
825103/0(1179 is shown in Table 2, for
the benefit of those who want to
analyse the logic functions involved in
producing the S-100 signals. Note that
device inputs 14, 15 and IF are not used,
and can be left unconnected; similarly
the ninth device output F8 is not used.
Note also that inputs 16 to IE inclusive
are all effectively programmed to act as
active-high enable inputs, so that they
must all be taken to logic high level for
any output to be enabled.
What this means is that these inputs
may effectively be used to disable the
5-100 interface, whenever the
processor is dealing with the memory
and I/O ports provided in the original
2650 system. This is done simply by connecting
active-low enable signals from
the existing 2650 system to some of the
825103 enable inputs, as shown. The
remaining enable inputs are simply tied