DRAM Technology

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Devices inside DRAM Chip Cell Cell Transistor Cell Capacitor Word line, Bit line, Contacts 1 MAT Cell Array Bit line sense amp Sub WL driver Peripheral Transistors High speed/ Low power S/A Transistor for Sensing SWD Transistor for driving WL with High Voltage Transistors for voltage generation Role Area Ratio Cell Data storage 50~55 % Core Data restoring 25~30 % peripheral Control-logic / In-Out interface ~20 % DRAM Technology SK hynix Lecture for POSTECH Page 22 Word Line Bit Line
DRAM Cell Word Line SN SN SN Gate Cell capacitor (Charge storage) Si BL Bit Line capacitor 1. Word Line Access Transistor Gate Control ( On/Off ) Storage Node High Data 보다 승압된 젂원 Level 사용 Poly-Si Layer (또는 WSi 2, W) 2. Bit Line Data Transfer Line Read/Write 공용 Half Vcore level Precharge for Power Saving 3. Access Transistor Switch기능의 NMOS Transistor 1개 Refresh 특성강화 위해 High Vt 설정 4. Capacitor Data 저장 장소 Storage Node의 Charge량에 의해 Data유지 REFRESH 필요 DRAM Technology SK hynix Lecture for POSTECH Page 23
Page 1 and 2: DRAM Technology Research & Developm
Page 3 and 4: Contents • Overview • DRAM Fund
Page 5 and 6: Chips DRAM Technology SK hynix Lect
Page 7 and 8: Classification of Memory DRAM Techn
Page 9 and 10: History of DRAM Dr. Robert H. Denn
Page 11 and 12: DRAM Producer ▷ Elpida ▷ Hynix
Page 13 and 14: DRAM Scaling Trend Minimum Feature
Page 15 and 16: DRAM 제품 제조 과정 Design Ci
Page 17 and 18: What is MOSFET ? Source 0V Gate Gat
Page 19 and 20: NMOS & PMOS Structure Vs NMOSFET PM
Page 21: DRAM Chip Architecture 1 MAT Cell A
Page 25 and 26: Basic DRAM operation Capacitor (Cs)
Page 27 and 28: Basic Operation : Write V PP Total
Page 29 and 30: Basic Operation : Retention Field O
Page 31 and 32: DRAM Scaling • Scaling Methods
Page 33 and 34: Scaling 1. Design Rule . 80nm → 6
Page 35 and 36: Folded vs. Open BL Scheme SA Scheme
Page 37 and 38: DRAM Technology Node Scaling Challe
Page 39 and 40: Cell Transistor : Considerations on
Page 41 and 42: Why Scaling ? T pd CV I C ox WLV
Page 43 and 44: MOSFET Scaling Method S Wd eff COX
Page 45 and 46: How to Increase the Transistor Perf
Page 47 and 48: Homework 1. “Peripheral Transisto

DRAM Technology

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