DRAM Technology

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Cell Transistor : History & Future Trends Cell Area [um2] 0.2 0.1 0.05 0.01 0.005 0.003 0.002 Planar Cell C-Halo Recess Gate 8F2 8F2 Sphere RG 150 120 100 80 60 50 40 30 20 6F2 6F2 Gate Active Saddle Fin FET Buried Gate 4F2 Vertical Gate 4F2 DRAM Technology SK hynix Lecture for POSTECH Page 40
Why Scaling ? T pd CV I C ox WLV W eff C ox L ( V V th ) Lateral scaling Iop ↑, Cap. ↓ Higher density Higher performance Low Power Vertical scaling Vt ↓/ St ↑/△Vt↑/μ↓ Ig↑/Cj↑/Rs↑ DRAM Technology SK hynix Lecture for POSTECH Page 41
Page 1 and 2: DRAM Technology Research & Developm
Page 3 and 4: Contents • Overview • DRAM Fund
Page 5 and 6: Chips DRAM Technology SK hynix Lect
Page 7 and 8: Classification of Memory DRAM Techn
Page 9 and 10: History of DRAM Dr. Robert H. Denn
Page 11 and 12: DRAM Producer ▷ Elpida ▷ Hynix
Page 13 and 14: DRAM Scaling Trend Minimum Feature
Page 15 and 16: DRAM 제품 제조 과정 Design Ci
Page 17 and 18: What is MOSFET ? Source 0V Gate Gat
Page 19 and 20: NMOS & PMOS Structure Vs NMOSFET PM
Page 21 and 22: DRAM Chip Architecture 1 MAT Cell A
Page 23 and 24: DRAM Cell Word Line SN SN SN Gate C
Page 25 and 26: Basic DRAM operation Capacitor (Cs)
Page 27 and 28: Basic Operation : Write V PP Total
Page 29 and 30: Basic Operation : Retention Field O
Page 31 and 32: DRAM Scaling • Scaling Methods
Page 33 and 34: Scaling 1. Design Rule . 80nm → 6
Page 35 and 36: Folded vs. Open BL Scheme SA Scheme
Page 37 and 38: DRAM Technology Node Scaling Challe
Page 39: Cell Transistor : Considerations on
Page 43 and 44: MOSFET Scaling Method S Wd eff COX
Page 45 and 46: How to Increase the Transistor Perf
Page 47 and 48: Homework 1. “Peripheral Transisto

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