DRAM Technology

More documents

Recommendations

Info

Types of Transistors Type of Transistor Applied Voltage Gate Oxide Thickness Gate Length Contact Key Requirements Cell Transistor VPP ( ~ 3.0V) VDD (1.5V @DDR3) Peripheral Transistors Normal Transistor BLSA Latch Transistor SWD Transistor Vcore ( 1.0~1.3V @DDR3) VPP (~3.0V) Thick Oxide Slim Oxide Thick Oxide Minimum Feature Size (ex. 45nm) Self-aligned contact with minimum gate spacer Low Junction leakage Short channel margin High operating current Minimum Lg in the peripheral circuit (ex. ≥ 80nm) Maximize Lg within pitched layout (ex. ≥ 120nm) Maximize Lg within pitched layout (ex. ≥ 140nm) Hole or Slit contact High Speed Short channel margin Small local variation Good Reliability DRAM Technology SK hynix Lecture for POSTECH Page 36
DRAM Technology Node Scaling Challenges of DRAM Technology 50nm 40nm 30nm 20nm 10nm Patterning Cell Capacitor Retention Time Sensing Margin Parasitic resistance Gate Oxide of Peri Tr Big Challenges ! 2008 2009 2010 2011 2012 2013 2014 2015 DRAM Technology SK hynix Lecture for POSTECH Page 37 Year
Page 1 and 2: DRAM Technology Research & Developm
Page 3 and 4: Contents • Overview • DRAM Fund
Page 5 and 6: Chips DRAM Technology SK hynix Lect
Page 7 and 8: Classification of Memory DRAM Techn
Page 9 and 10: History of DRAM Dr. Robert H. Denn
Page 11 and 12: DRAM Producer ▷ Elpida ▷ Hynix
Page 13 and 14: DRAM Scaling Trend Minimum Feature
Page 15 and 16: DRAM 제품 제조 과정 Design Ci
Page 17 and 18: What is MOSFET ? Source 0V Gate Gat
Page 19 and 20: NMOS & PMOS Structure Vs NMOSFET PM
Page 21 and 22: DRAM Chip Architecture 1 MAT Cell A
Page 23 and 24: DRAM Cell Word Line SN SN SN Gate C
Page 25 and 26: Basic DRAM operation Capacitor (Cs)
Page 27 and 28: Basic Operation : Write V PP Total
Page 29 and 30: Basic Operation : Retention Field O
Page 31 and 32: DRAM Scaling • Scaling Methods
Page 33 and 34: Scaling 1. Design Rule . 80nm → 6
Page 35: Folded vs. Open BL Scheme SA Scheme
Page 39 and 40: Cell Transistor : Considerations on
Page 41 and 42: Why Scaling ? T pd CV I C ox WLV
Page 43 and 44: MOSFET Scaling Method S Wd eff COX
Page 45 and 46: How to Increase the Transistor Perf
Page 47 and 48: Homework 1. “Peripheral Transisto

DRAM Technology

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?