DRAM Technology

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Cell Area Factor toward more compact Unit Cell Area 8F 2 6F 2 4F 2 Schematic Special Feature Normal Twist Tr Vertical Tr Sensing Folded Open Open Cell Cap. Area 4F 2 3F 2 2F 2 S/A Pitch 4 BL Pitch 2 BL Pitch 2 BL pitch Merits WL BL SNC BLC 2F Noise immunity Large Cs Demerits Large cell size Active area 4F 2F WL BL 3F Medium cell Small Cb WL 2F Large noise BL Integration difficulty 2F Small cell Small Cb DRAM Technology SK hynix Lecture for POSTECH Page 34
Folded vs. Open BL Scheme SA Scheme Folded Bit line (8F 2 ) Open Bit line (4/6F 2 ) SA SA SA Cell Architecture 6F 2 Layout DRAM Technology SK hynix Lecture for POSTECH Page 35
Page 1 and 2: DRAM Technology Research & Developm
Page 3 and 4: Contents • Overview • DRAM Fund
Page 5 and 6: Chips DRAM Technology SK hynix Lect
Page 7 and 8: Classification of Memory DRAM Techn
Page 9 and 10: History of DRAM Dr. Robert H. Denn
Page 11 and 12: DRAM Producer ▷ Elpida ▷ Hynix
Page 13 and 14: DRAM Scaling Trend Minimum Feature
Page 15 and 16: DRAM 제품 제조 과정 Design Ci
Page 17 and 18: What is MOSFET ? Source 0V Gate Gat
Page 19 and 20: NMOS & PMOS Structure Vs NMOSFET PM
Page 21 and 22: DRAM Chip Architecture 1 MAT Cell A
Page 23 and 24: DRAM Cell Word Line SN SN SN Gate C
Page 25 and 26: Basic DRAM operation Capacitor (Cs)
Page 27 and 28: Basic Operation : Write V PP Total
Page 29 and 30: Basic Operation : Retention Field O
Page 31 and 32: DRAM Scaling • Scaling Methods
Page 33: Scaling 1. Design Rule . 80nm → 6
Page 37 and 38: DRAM Technology Node Scaling Challe
Page 39 and 40: Cell Transistor : Considerations on
Page 41 and 42: Why Scaling ? T pd CV I C ox WLV
Page 43 and 44: MOSFET Scaling Method S Wd eff COX
Page 45 and 46: How to Increase the Transistor Perf
Page 47 and 48: Homework 1. “Peripheral Transisto

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