DRAM Technology

More documents

Recommendations

Info

Shrink Limitations : Transistor Cell Tr Peri Tr Planar WSix N+ BC-PMOS Recessed Fin Vertical Nanowire WSix P+ SC-PMOS P+ 100 100 80 80 60 40 40 20 1020 W W-SC Technology (nm) Technology Node (nm) W P+ Strained / ESD Fin /HKMG DRAM Technology SK hynix Lecture for POSTECH Page 38
Cell Transistor : Considerations on Scaling Lower Retention time caused by increased electric field. Lower On-Current caused by decreased dimension. Higher Off-Leakage current caused by short channel effect. [Source : S.Y. Cha(Hynix), VLSI Short Course 2011] Process margin D/R Refresh Time On-Current Off-Leakage Scale down How to increase retention time ? How to increase on-current ? How to improve short channel margin ? DRAM Technology SK hynix Lecture for POSTECH Page 39
Page 1 and 2: DRAM Technology Research & Developm
Page 3 and 4: Contents • Overview • DRAM Fund
Page 5 and 6: Chips DRAM Technology SK hynix Lect
Page 7 and 8: Classification of Memory DRAM Techn
Page 9 and 10: History of DRAM Dr. Robert H. Denn
Page 11 and 12: DRAM Producer ▷ Elpida ▷ Hynix
Page 13 and 14: DRAM Scaling Trend Minimum Feature
Page 15 and 16: DRAM 제품 제조 과정 Design Ci
Page 17 and 18: What is MOSFET ? Source 0V Gate Gat
Page 19 and 20: NMOS & PMOS Structure Vs NMOSFET PM
Page 21 and 22: DRAM Chip Architecture 1 MAT Cell A
Page 23 and 24: DRAM Cell Word Line SN SN SN Gate C
Page 25 and 26: Basic DRAM operation Capacitor (Cs)
Page 27 and 28: Basic Operation : Write V PP Total
Page 29 and 30: Basic Operation : Retention Field O
Page 31 and 32: DRAM Scaling • Scaling Methods
Page 33 and 34: Scaling 1. Design Rule . 80nm → 6
Page 35 and 36: Folded vs. Open BL Scheme SA Scheme
Page 37: DRAM Technology Node Scaling Challe
Page 41 and 42: Why Scaling ? T pd CV I C ox WLV
Page 43 and 44: MOSFET Scaling Method S Wd eff COX
Page 45 and 46: How to Increase the Transistor Perf
Page 47 and 48: Homework 1. “Peripheral Transisto

DRAM Technology

Create successful ePaper yourself

Delete template?

Save as template?