hardware implementation of data compression ... - INFN Bologna

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114 2D compression algorithm and implementation – indat0 : input 15-bit bus; – trigger-data: input 12-bit bus; – reset: input signal; – ck: input signal; – gol-ready: input signal; – fifo-empty: input 2-bit bus; – half-ladder-id: input 7-bit bus; – all-fifos-empty: input signal; – event-id: input 3-bit bus; – no-input-data: input signal; – event-identifier: output signal; – read-data: output 2-bit bus; – read-trigger: output signal; – output-strobe: output signal; – output: output 16-bit bus. The outmux block is a multiplexing unit for sending in output data coming from the two main processing channels in an interlaced way, meaning that during the even clock periods data coming from channel 1 are put in output, while during the odd clock periods data coming from channel 0 are served. This is the way the outmux block behaves: as soon as data begin to fill the two FIFO blocks the outmux block begins to put in output a packet like the one shown in Fig. 4.11. The first 3 16-bit words contain trigger informations coming from the trigger channel, the first word contains the bunch counter, while second and third word contain event counter MSBs and LSBs respectively. Since trigger informations are 12-bit long they are added the bits 1011 as MSBs in order to be able to recognize them easily in a later phase of data reconstruction. Follow two header words containing the local event-id number and the
4.5 — CARLOS v3 building blocks Figure 4.11: CARLOS v3 data transmission protocol externally hardwired information half-ladder-id. The MSBs from the header word are 110. Headers are followed by an even number of data words containing data from the two main channels: if a channel has not valid data to send, the MSB is put to 1 and all the other bits are set to 0, meaning that a dummy data is sent in output, otherwise the MSB is set to 0 meaning that the data word is valid. The data packet is then concluded with the transmission of two footer words containing the same information of the header regarding the event-id number and the number of words being sent in output. The MSBs are set to 1, so to uniquely identify the footer word type. The outmux block puts in output the 16-bit data words and the signal output-strobe. When this signal is high, CARLOS is transmitting data belonging to a packet, while when low CARLOS is not sending useful 115
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UNIVERSITÀ DEGLI STUDI DI BOLOGNA
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Contents Introduction ix 1 The ALIC
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CONTENTS 4 2D compression algorithm
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Introduction This thesis work has b
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Chapter 1 The ALICE experiment ALIC
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1.1 — The Inner Tracking System 1
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1.1 — The Inner Tracking System t
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1.1 — The Inner Tracking System P
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1.2 — Design of the drift layers
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1.3 — The SDDs (Silicon Drift Det
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PASCAL AMBRA 1.4 — SDD readout sy
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data_in[0] data_in[1] data_in[2] da
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1.4 — SDD readout system 1.4.2 Ev
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1.4 — SDD readout system with a c
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Chapter 2 Data compression techniqu
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2.2 — Remarks on information theo
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2.3 — Compression techniques 2.3.
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2.4 — Lossless compression techni
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Original sequence Sequence after di
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2.5 — Lossy compression technique
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2.6 — Implementation of compressi
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Symlets sym2 sym3 sym4 sym8 Wavelet
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Chapter 3 1D compression algorithm
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3.2 — 1D compression algorithm Fi
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3.3 — 1D algorithm performances s
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3.3 — 1D algorithm performances F
Page 75 and 76: 3.4 — CARLOS v1 Figure 3.6: CARLO
Page 77 and 78: 3.4 — CARLOS v1 Figure 3.7: Pictu
Page 79 and 80: 3.4 — CARLOS v1 3.4.3 Functions p
Page 81 and 82: 3.5 — CARLOS v2 have a 100% compa
Page 83 and 84: 3.5 — CARLOS v2 3.5.1 The firstch
Page 85 and 86: 3.5 — CARLOS v2 data and when loa
Page 87 and 88: 3.5 — CARLOS v2 which of the 8 qu
Page 89 and 90: - indat6 : input 32-bit bus; - inda
Page 91 and 92: 3.5 — CARLOS v2 - femux is a mult
Page 93 and 94: 3.5 — CARLOS v2 total optical fib
Page 95 and 96: 3.5 — CARLOS v2 Figure 3.11: Desi
Page 97 and 98: 3.5 — CARLOS v2 that CARLOS will
Page 99 and 100: 3.6 — CARLOS v2 design flow Figur
Page 101 and 102: 3.7 — Tests performed on CARLOS v
Page 103 and 104: Chapter 4 2D compression algorithm
Page 105 and 106: 4.1 — 2D compression algorithm Fi
Page 111 and 112: 4.2 — CARLOS v3 vs. the previous
Page 113 and 114: 4.3 — The final readout architect
Page 115 and 116: 4.5 — CARLOS v3 building blocks -
Page 117 and 118: 4.5 — CARLOS v3 building blocks T
Page 119 and 120: 4.5 — CARLOS v3 building blocks F
Page 121 and 122: 4.5 — CARLOS v3 building blocks c
Page 123 and 124: 4.5 — CARLOS v3 building blocks F
Page 125: 4.5 — CARLOS v3 building blocks o
Page 129 and 130: 4.5 — CARLOS v3 building blocks u
Page 131 and 132: 4.5 — CARLOS v3 building blocks a
Page 133 and 134: 4.5 — CARLOS v3 building blocks p
Page 135 and 136: 4.7 — CARLOS layout features post
Page 137 and 138: Chapter 5 Wavelet based compression
Page 139 and 140: levels used: 5.1 — Wavelet based
Page 141 and 142: 5.2 — Multiresolution algorithm o
Page 153 and 154: 5.3 — Choice of the architecture
Page 155 and 156: 5.3 — Choice of the architecture
Page 157 and 158: Dettaglio 1 1 D1 2 Downsample Hi_De
Page 159 and 160: 2 Upsample Dettaglio 1 1 D1 Hi_Rec
Page 161 and 162: 5.4 — Multiresolution algorithm p
Page 163 and 164: 5.5 — Hardware implementation ter
Page 165 and 166: 5.5 — Hardware implementation Fig
Page 167 and 168: 5.5 — Hardware implementation com
Page 169 and 170: 5.5 — Hardware implementation Haa
Page 171 and 172: Conclusions The main goal of this t
Page 173 and 174: Bibliography [1] ALICE Collaboratio
Page 175: BIBLIOGRAPHY [19] D. Cavagnino, P.
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