hardware implementation of data compression ... - INFN Bologna

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144 Wavelet based <strong>compression</strong> algorithm D1 D2 D1 del D2 del D1 D2 D3 D4 D3 del D4 del D3 D4 D5 D6 D5 del D6 del D5 D6 D7 D8 D7 del D8 del D7 D8 R Segnale Ricostruito D9 D10 D9 del D10 del D9 D10 Segnale S Segnale Ricostruito D11 del D12 del D11 D12 Segnale D13 del D14 del D13 D14 D15 del D16 del D15 D16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 A16 Figure 5.3: Developed Simulink blocks: from left to right the analysis block, the delay block and the threshold and synthesis block D11 D12 D13 D14 D15 D16 A16 A16 del A16 Applicazione soglia e 16 livelli di sintesi Delay 16 livelli di analisi
Dettaglio 1 1 D1 2 Downsample Hi_Dec Filter 1 Segnale 2 Downsample1 Low_Dec Filter Dettaglio 2 2 D2 2 Downsample2 Hi_Dec Filter1 2 Downsample3 Low_Dec Filter1 Dettaglio 3 3 D3 2 Downsample4 Hi_Dec Filter2 Dettaglio 6 6 D6 2 2 Downsample5 Low_Dec Filter2 Downsample10 Hi_Dec Filter5 Dettaglio 4 4 D4 2 Downsample6 Hi_Dec Filter3 5.3 — Choice <strong>of</strong> the architecture 2 Downsample7 Low_Dec Filter3 2 Dettaglio 5 5 D5 2 Downsample8 Hi_Dec Filter4 Downsample11 Low_Dec Filter5 2 Downsample9 Low_Dec Filter4 Dettaglio 6 6 D6 2 Downsample10 Hi_Dec Filter5 2 Downsample11 Low_Dec Filter5 Dettaglio 7 7 D7 2 Downsample12 Hi_Dec Filter6 2 Downsample13 Low_Dec Filter6 Dettaglio 8 8 D8 2 Downsample14 Hi_Dec Filter7 Figure 5.4: Zoom on the developed analysis block 2 Downsample15 Low_Dec Filter7 Dettaglio 9 9 D9 2 Downsample16 Hi_Dec Filter8 2 Downsample17 Low_Dec Filter8 Dettaglio 10 10 D10 2 Downsample18 Hi_Dec Filter9 2 Downsample19 Low_Dec Filter9 Dettaglio 11 11 D11 2 Downsample20 Hi_Dec Filter10 2 Downsample21 Low_Dec Filter10 Dettaglio 12 12 D12 2 Downsample22 Hi_Dec Filter11 2 Downsample23 Low_Dec Filter11 Dettaglio 13 13 D13 2 Downsample24 Hi_Dec Filter12 2 Downsample25 Low_Dec Filter12 Dettaglio 14 14 D14 2 Downsample26 Hi_Dec Filter13 2 Downsample27 Low_Dec Filter13 Dettaglio 15 15 D15 2 Downsample28 Hi_Dec Filter14 2 Downsample29 Low_Dec Filter14 Dettaglio 16 16 D16 2 Downsample30 Hi_Dec Filter15 Approssimazione 16 17 A16 2 Downsample31 Low_Dec Filter15 145
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UNIVERSITÀ DEGLI STUDI DI BOLOGNA
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Contents Introduction ix 1 The ALIC
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CONTENTS 4 2D compression algorithm
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Introduction This thesis work has b
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Chapter 1 The ALICE experiment ALIC
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1.1 — The Inner Tracking System 1
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1.1 — The Inner Tracking System t
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1.1 — The Inner Tracking System P
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1.2 — Design of the drift layers
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1.3 — The SDDs (Silicon Drift Det
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PASCAL AMBRA 1.4 — SDD readout sy
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data_in[0] data_in[1] data_in[2] da
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1.4 — SDD readout system 1.4.2 Ev
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1.4 — SDD readout system with a c
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Chapter 2 Data compression techniqu
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2.2 — Remarks on information theo
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2.3 — Compression techniques 2.3.
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2.4 — Lossless compression techni
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Original sequence Sequence after di
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2.5 — Lossy compression technique
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2.6 — Implementation of compressi
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Symlets sym2 sym3 sym4 sym8 Wavelet
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Chapter 3 1D compression algorithm
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3.2 — 1D compression algorithm Fi
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3.3 — 1D algorithm performances s
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3.3 — 1D algorithm performances F
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3.4 — CARLOS v1 Figure 3.6: CARLO
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3.4 — CARLOS v1 Figure 3.7: Pictu
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3.4 — CARLOS v1 3.4.3 Functions p
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3.5 — CARLOS v2 have a 100% compa
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3.5 — CARLOS v2 3.5.1 The firstch
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3.5 — CARLOS v2 data and when loa
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3.5 — CARLOS v2 which of the 8 qu
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- indat6 : input 32-bit bus; - inda
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3.5 — CARLOS v2 - femux is a mult
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3.5 — CARLOS v2 total optical fib
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3.5 — CARLOS v2 Figure 3.11: Desi
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3.5 — CARLOS v2 that CARLOS will
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3.6 — CARLOS v2 design flow Figur
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3.7 — Tests performed on CARLOS v
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Chapter 4 2D compression algorithm
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Page 111 and 112: 4.2 — CARLOS v3 vs. the previous
Page 113 and 114: 4.3 — The final readout architect
Page 115 and 116: 4.5 — CARLOS v3 building blocks -
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Page 119 and 120: 4.5 — CARLOS v3 building blocks F
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Page 131 and 132: 4.5 — CARLOS v3 building blocks a
Page 133 and 134: 4.5 — CARLOS v3 building blocks p
Page 135 and 136: 4.7 — CARLOS layout features post
Page 137 and 138: Chapter 5 Wavelet based compression
Page 139 and 140: levels used: 5.1 — Wavelet based
Page 141 and 142: 5.2 — Multiresolution algorithm o
Page 153 and 154: 5.3 — Choice of the architecture
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Page 159 and 160: 2 Upsample Dettaglio 1 1 D1 Hi_Rec
Page 161 and 162: 5.4 — Multiresolution algorithm p
Page 163 and 164: 5.5 — Hardware implementation ter
Page 165 and 166: 5.5 — Hardware implementation Fig
Page 167 and 168: 5.5 — Hardware implementation com
Page 169 and 170: 5.5 — Hardware implementation Haa
Page 171 and 172: Conclusions The main goal of this t
Page 173 and 174: Bibliography [1] ALICE Collaboratio
Page 175: BIBLIOGRAPHY [19] D. Cavagnino, P.
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