hardware implementation of data compression ... - INFN Bologna

3.6 — CARLOS v2 design flow
Figure 3.12: Digital design flow for CARLOS v2
1 only if all the local end-trace signals have been put to 1 for at least
one clock period in the current event. From the moment in which the
end-trace-global is asserted and when the all-fifos-empty is activated
no new input data set can enter CARLOS.
3.6 CARLOS v2 design flow
Fig. 3.12 illustrates the digital design flow for CARLOS v2. The front
end steps are exactly the same as the ones followed in the design of
CARLOS v1. The only difference is the library used, being, in this
case, the Alcatel Mietec 0.35 µm digital library provided via Europractice.
This is a very rich library since it contains more than 200
differents standard cells and RAM blocks with several dimensions. A
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