hardware implementation of data compression ... - INFN Bologna
hardware implementation of data compression ... - INFN Bologna
hardware implementation of data compression ... - INFN Bologna
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86<br />
1D <strong>compression</strong> algorithm and <strong>implementation</strong>s<br />
quisition system, or the SIU can leave the bidirectional buses control to<br />
CARLOS for an other <strong>data</strong> event to be sent. So far, CARLOS begins<br />
waiting 16 foclk periods: if nothing happens, CARLOS is able to begin<br />
sending <strong>data</strong> again without the need to receive some other commands<br />
from the SIU; if the SIU takes back the possession <strong>of</strong> the bidirectional<br />
buses, CARLOS closes the link towards the SIU and keeps waiting for<br />
an other RDYRX command raised from the SIU itself.<br />
The feesiu block implements this communication protocol with the SIU<br />
using a simple state-machine: for example state 0 is the state in which<br />
CARLOS is waiting for a command <strong>of</strong> initialization from the SIU, state<br />
1 is the state in which CARLOS sends <strong>data</strong> from the SIU, state 2 in<br />
which CARLOS sends the front end status word to the SIU, state 3<br />
in which CARLOS waits 16 foclk periods waiting for some action from<br />
the SIU to happen.<br />
An important feature <strong>of</strong> CARLOS realized in the feesiu blockisthe<br />
following one: CARLOS cannot accept a new event before the previous<br />
one has been completely sent in output, otherwise we run into the<br />
risk <strong>of</strong> mixing <strong>data</strong> belonging to different events. The only way CAR-<br />
LOS has to implement back-pressure on the AMBRA chips is using the<br />
wait-request signals. So far the wait-request signal has to avoid that<br />
CARLOS fetches new input <strong>data</strong> values while emptying the FIFOs.<br />
For this reason a new signal, dont-send-<strong>data</strong>, has been introduced for<br />
every macro-channel which turns to 1 when the end-trace is activated<br />
and turns back to 0 when all the FIFOs are completely empty. So<br />
the wait-request <strong>of</strong> every macro-channel is obtained by putting in OR<br />
the full and dont-send-<strong>data</strong> signals. The feesiu acknowledges that all<br />
the FIFOs have been emptied using the empty signal <strong>of</strong> every FIFO<br />
block. When all the 8 signals turn to 1 the feesiu block raises the allfifos-empty<br />
signal which stands at logical level 1 for at least two clock<br />
periods in order to be sensed by the foclk clock. The all-fifos-empty signal<br />
is also used to trigger the event-counter block: in fact the number<br />
<strong>of</strong> total events is exactly the same as the total number <strong>of</strong> occurrences<br />
<strong>of</strong> the all-fifos-empty signal. An other signal, end-trace-global is set to