hardware implementation of data compression ... - INFN Bologna

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viii CONTENTS 5.2.3 Choice of the dimensionality, number of levels and threshold value . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.3 Choice of the architecture . . . . . . . . . . . . . . . . . . . . 141 5.3.1 Simulink and the Fixed-Point Blockset . . . . . . . . . 141 5.3.2 Choice of the architecture . . . . . . . . . . . . . . . . 143 5.4 Multiresolution algorithm performances . . . . . . . . . . . . . 149 5.5 Hardware implementation . . . . . . . . . . . . . . . . . . . . 151 Conclusions 159 Bibliography 161
Introduction This thesis work has been aimed at the hardware implementation of data compression algorithms to be applied to High Energy Physics Experiments. The amount of data that will be produced by LHC experiments at CERN is of the order of magnitude of 1 GByte/s. Cost constraints on magnetic tapes and data acquisition systems (optical fibres, readout boards) require to apply on-line data compression on the front-end electronics of the different detectors. This leads to the search of the compression algorithms allowing to achieve a high compression ratio, while keeping low the value of the reconstruction error. In fact a high compression coefficient can only be achieved at the expense of some loss on the physical data. The thesis contains the description of the hardware implementation of compression algorithms applied to the ALICE experiment for what concerns the SDD (Silicon Drift Detector) readout chain. The total amount of data produced by SDDs is 32.5 MBytes per event, while the reserved space on magnetic tapes for permanent storage is 1.5 MBytes. This means that the compression coefficient has to be at least 22. Beside that, since the p-p interaction rate is 1000 Hz, data compression hardware has to complete its job within 1 ms. This leads to the search for high performances compression algorithms for what concerns both compression ratio and execution speed. The thesis contains a description of the design and implementation of 3 prototypes of the ASIC CARLOS (Compression And Run Length encOding Subsystem) which deals with the on-line data compression, packing and transmission to the standard ALICE data acquisition system. CARLOS v1 and v2 contain a uni-dimensional compression algorithm based on threshold, run length encoding, differential encoding and Huffman coding techniques. ix
Page 1: UNIVERSITÀ DEGLI STUDI DI BOLOGNA
Page 5 and 6: Contents Introduction ix 1 The ALIC
Page 7: CONTENTS 4 2D compression algorithm
Page 13 and 14: Chapter 1 The ALICE experiment ALIC
Page 15 and 16: 1.1 — The Inner Tracking System 1
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Page 21 and 22: 1.2 — Design of the drift layers
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Page 27 and 28: data_in[0] data_in[1] data_in[2] da
Page 29 and 30: 1.4 — SDD readout system 1.4.2 Ev
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Page 37 and 38: 2.3 — Compression techniques 2.3.
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2.5 — Lossy compression technique
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2.5 — Lossy compression technique
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2.6 — Implementation of compressi
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Symlets sym2 sym3 sym4 sym8 Wavelet
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Chapter 3 1D compression algorithm
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3.2 — 1D compression algorithm Fi
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3.3 — 1D algorithm performances s
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3.3 — 1D algorithm performances F
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3.4 — CARLOS v1 Figure 3.6: CARLO
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3.4 — CARLOS v1 Figure 3.7: Pictu
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3.4 — CARLOS v1 3.4.3 Functions p
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3.5 — CARLOS v2 have a 100% compa
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3.5 — CARLOS v2 3.5.1 The firstch
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3.5 — CARLOS v2 data and when loa
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3.5 — CARLOS v2 which of the 8 qu
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- indat6 : input 32-bit bus; - inda
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3.5 — CARLOS v2 - femux is a mult
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3.5 — CARLOS v2 total optical fib
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3.5 — CARLOS v2 Figure 3.11: Desi
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3.5 — CARLOS v2 that CARLOS will
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3.6 — CARLOS v2 design flow Figur
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3.7 — Tests performed on CARLOS v
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Chapter 4 2D compression algorithm
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4.2 — CARLOS v3 vs. the previous
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4.3 — The final readout architect
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4.5 — CARLOS v3 building blocks -
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4.5 — CARLOS v3 building blocks T
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4.5 — CARLOS v3 building blocks F
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4.5 — CARLOS v3 building blocks c
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4.5 — CARLOS v3 building blocks o
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4.5 — CARLOS v3 building blocks u
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4.5 — CARLOS v3 building blocks a
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4.5 — CARLOS v3 building blocks p
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4.7 — CARLOS layout features post
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Chapter 5 Wavelet based compression
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levels used: 5.1 — Wavelet based
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5.2 — Multiresolution algorithm o
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5.3 — Choice of the architecture
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5.3 — Choice of the architecture
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Dettaglio 1 1 D1 2 Downsample Hi_De
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2 Upsample Dettaglio 1 1 D1 Hi_Rec
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5.4 — Multiresolution algorithm p
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5.5 — Hardware implementation ter
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5.5 — Hardware implementation Fig
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5.5 — Hardware implementation com
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5.5 — Hardware implementation Haa
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Conclusions The main goal of this t
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Bibliography [1] ALICE Collaboratio
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BIBLIOGRAPHY [19] D. Cavagnino, P.
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