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Integrated Circuit Outlier Identification by Multiple Parameter Correlation Sagar Sabade Department of Computer Science <strong>Texas</strong> A&M <strong>University</strong>, MS 3112 College Station, TX 77843-3112 E-mail: sagar@tamu.edu
Outline Introduction Problem Definition Prior Work Research Goals Research Plan Summary
Page 1: “Research is to see what everyone
Page 5 and 6: Smaller Needle, Bigger Haystack ©
Page 7 and 8: Basic Testing Methodology Input 1 0
Page 9 and 10: IC Testing Methods Functional test
Page 11 and 12: Leakage Current (I DDQ) Test Prima
Page 13 and 14: Defect Types Active (pattern-depen
Page 15 and 16: Conventional I DDQ Testing Single
Page 17 and 18: ITRS Projections for I DDQ Year Gat
Page 19 and 20: I DDQ and Defect Severity Frequency
Page 21 and 22: I DDQ Only a Part of the Puzzle Inc
Page 23 and 24: Why Use Outlier Detection? Continu
Page 25 and 26: Outlier Identification Methods Rel
Page 27 and 28: Frequency No Silver Bullet 180 160
Page 29 and 30: Approach 1: Reducing Fault-free I D
Page 31 and 32: Die 1 I DDQ Variation Level 2 Level
Page 33 and 34: Die 1 and Die 2 I DDQ Variation Die
Page 35 and 36: Four Dice From a Wafer Difficult to
Page 37 and 38: Current Signature [Gattiker,Maly]
Page 39 and 40: Differential/Delta I DDQ [Thibeault
Page 41 and 42: Current Ratios [Maxwell et al.] CR
Page 43 and 44: Threshold Selection Challenge Max I
Page 45 and 46: Motivation: Spatial Correlation Si
Page 47 and 48: Local Neighborhood Definition Cente
Page 49 and 50: Correlation Methods Spatial/plane
Page 51 and 52: Neighbor Current Ratios (NCR) Two
Page 53 and 54:
Max NCR Max NCR CR/NCR Insights 100
Page 55 and 56:
Immediate Neighbor Difference I DDQ
Page 57 and 58:
I DDQ & Flush Delay Correlation Flu
Page 59 and 60:
Research Plan - I Extensive analys
Page 61 and 62:
Research Contributions Systematic
Page 63 and 64:
Summary Defect-based VLSI testing
Page 65 and 66:
Backup Slides
Page 67 and 68:
I/P Pattern Independent Defect O/P
Page 69 and 70:
Process Variation Levels Frequency
Page 71 and 72:
Technology Impact on Testing Reduc
Page 73 and 74:
Scaling Implications on IOFF I OFF
Page 75 and 76:
Non-uniform Scaling Trends Source :
Page 77 and 78:
“All Pass” Chips I DDQ Variatio
Page 79 and 80:
Leakage Current Components Input =
Page 81 and 82:
Major I DDQ Components I D (Log sca
Page 83 and 84:
Two Signature Types IDDQ (uA) 54.5
Page 85 and 86:
Handling Defect Clustering Scratch
Page 87 and 88:
Why I DDQ Correlates to Delay? Sma
Page 89 and 90:
All Tests Are Needed Distribution o
Page 91 and 92:
Fewer Vectors,Higher Coverage Fault
Page 93 and 94:
Wafer-level Analysis: Advantages D
Page 95 and 96:
Delta I DDQ Illustration First meas
Page 97 and 98:
Technology Trends
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presentation slides - Texas A&M University

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