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Optimum Threshold Selection Frequency Cost vs. Quality debate Zero Test Escapes High Overkill Optimum Threshold I DDQ Fault-free chips Faulty chips Zero Yield Loss High Defect Level
Wafer-level Analysis: Advantages Detection of defective chips at wafer probe Reduction in test costs and time Reduced packaging cost/die Provides insight into understanding underlying process variations Useful for detecting process glitches Different pass/fail criterion for different wafers Reduce yield penalty for fast and leaky wafers
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“Research is to see what everyone
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Outline Introduction Problem Defi
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Smaller Needle, Bigger Haystack ©
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Basic Testing Methodology Input 1 0
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IC Testing Methods Functional test
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Leakage Current (I DDQ) Test Prima
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Defect Types Active (pattern-depen
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Conventional I DDQ Testing Single
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ITRS Projections for I DDQ Year Gat
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I DDQ and Defect Severity Frequency
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I DDQ Only a Part of the Puzzle Inc
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Why Use Outlier Detection? Continu
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Outlier Identification Methods Rel
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Frequency No Silver Bullet 180 160
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Approach 1: Reducing Fault-free I D
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Die 1 I DDQ Variation Level 2 Level
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Die 1 and Die 2 I DDQ Variation Die
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Four Dice From a Wafer Difficult to
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Current Signature [Gattiker,Maly]
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Differential/Delta I DDQ [Thibeault
Page 41 and 42: Current Ratios [Maxwell et al.] CR
Page 43 and 44: Threshold Selection Challenge Max I
Page 45 and 46: Motivation: Spatial Correlation Si
Page 47 and 48: Local Neighborhood Definition Cente
Page 49 and 50: Correlation Methods Spatial/plane
Page 51 and 52: Neighbor Current Ratios (NCR) Two
Page 53 and 54: Max NCR Max NCR CR/NCR Insights 100
Page 55 and 56: Immediate Neighbor Difference I DDQ
Page 57 and 58: I DDQ & Flush Delay Correlation Flu
Page 59 and 60: Research Plan - I Extensive analys
Page 61 and 62: Research Contributions Systematic
Page 63 and 64: Summary Defect-based VLSI testing
Page 65 and 66: Backup Slides
Page 67 and 68: I/P Pattern Independent Defect O/P
Page 69 and 70: Process Variation Levels Frequency
Page 71 and 72: Technology Impact on Testing Reduc
Page 73 and 74: Scaling Implications on IOFF I OFF
Page 75 and 76: Non-uniform Scaling Trends Source :
Page 77 and 78: “All Pass” Chips I DDQ Variatio
Page 79 and 80: Leakage Current Components Input =
Page 81 and 82: Major I DDQ Components I D (Log sca
Page 83 and 84: Two Signature Types IDDQ (uA) 54.5
Page 85 and 86: Handling Defect Clustering Scratch
Page 87 and 88: Why I DDQ Correlates to Delay? Sma
Page 89 and 90: All Tests Are Needed Distribution o
Page 91: Fewer Vectors,Higher Coverage Fault
Page 95 and 96: Delta I DDQ Illustration First meas
Page 97 and 98: Technology Trends
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presentation slides - Texas A&M University

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