Chapter 22 Multichannel Audio Serial Port (McASP).pdf

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22.3.3.2.3 Frame Format
An S/PDIF frame is composed of two subframes (Figure 22-13). For linear coded audio applications, the
rate of frame transmission normally corresponds exactly to the source sampling frequency f s. The S/PDIF
format clock rate is therefore 128 × f s (128 = 32 cells/subframe × 2 clocks/cell × 2 subframes/sample). For
example, for an S/PDIF stream at a 192 kHz sampling frequency, the serial clock is
128 × 192 kHz = 24.58 MHz.
In 2-channel operation mode, the samples taken from both channels are transmitted by time multiplexing
in consecutive subframes. Both subframes contain valid data. The first subframe (left or A channel in
stereophonic operation and primary channel in monophonic operation) normally starts with preamble M.
However, the preamble of the first subframe changes to preamble B once every 192 frames to identify the
start of the block structure used to organize the channel status information. The second subframe (right or
B channel in stereophonic operation and secondary channel in monophonic operation) always starts with
preamble W.
In single-channel operation mode in a professional application, the frame format is the same as in the 2channel
mode. Data is carried in the first subframe and may be duplicated in the second subframe. If the
second subframe is not carrying duplicate data, cell 28 (validity bit) is set to logical 1.
X Y Z Y X Y X
M Channel
1
Frame 191
22.3.4 Definition of Terms
Figure 22-13. S/PDIF Frame Format
Channel
W W
2
Channel
Channel
B
1
2
Subframe 1
Frame 0
Subframe 2
Channel Channel
M W
M
1
2
Frame 1
The serial bit stream transmitted or received by the McASP is a long sequence of 1s and 0s, either output
or input on one of the audio transmit/receive pins (AXRn). However, the sequence has a hierarchical
organization that can be described in terms of frames of data, slots, words, and bits.
A basic synchronous serial interface consists of three important components: clock, frame sync, and data.
Figure 22-14 shows two of the three basic components—the clock (ACLK) and the data (AXRn).
Figure 22-14 does not specify whether the clock is for transmit (ACLKX) or receive (ACLKR) because the
definitions of terms apply to both receive and transmit interfaces. In operation, the transmitter uses ACLKX
as the serial clock, and the receiver uses ACLKR as the serial clock. Optionally, the receiver can use
ACLKX as the serial clock when the transmitter and receiver of the McASP are configured to operate
synchronously.
Bit A bit is the smallest entity in the serial data stream. The beginning and end of each bit is marked by an edge of the
serial clock. The duration of a bit is a serial clock period. A 1 is represented by a logic high on the AXRn pin for the
entire duration of the bit. A 0 is represented by a logic low on the AXRn pin for the entire duration of the bit.
Word A word is a group of bits that make up the data being transferred between the processor and the external device.
Figure 22-14 shows an 8-bit word.
Slot A slot consists of the bits that make up the word, and may consist of additional bits used to pad the word to a
convenient number of bits for the interface between the processor and the external device. In Figure 22-14, the
audio data consists of only 8 bits of useful data (8-bit word), but it is padded with 4 zeros (12-bit slot) to satisfy the
desired protocol in interfacing to an external device. Within a slot, the bits may be shifted in/out of the McASP on the
AXRn pin either MSB or LSB first. When the word size is smaller than the slot size, the word may be aligned to the
left (beginning) of the slot or to the right (end) of the slot. The additional bits in the slot not belonging to the word
may be padded with 0, 1, or with one of the bits (the MSB or the LSB typically) from the data word. These options
are shown in Figure 22-15.
3938 Multichannel Audio Serial Port (McASP) SPRUH73E–October 2011–Revised May 2012
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