Chapter 22 Multichannel Audio Serial Port (McASP).pdf

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Integration www.ti.com 22.2 Integration The device contains two instantiations of the McASP subsystem: McASP0 and McASP1. The McASP subsystem includes a McASP peripheral, and transmit/receive buffers. Each McASP is configured with four serializers. CLK_M_OSC L3 Slow Interconnect L4 Peripheral Interconnect MPU Subsystem and PRU-ICSS Interrupts EDMA PRCM 22.2.1 McASP Connectivity Attributes Figure 22-1. McASP0–1 Integration AXEVT0 AREVT0 MCASP_FCLK DMA/Data 12 TINT Interface McASP Subsystem TINT 34 CFG Interface x_intr_pend r_intr_pend xevent_dreq revent_dreq aux_clk AHCLKX MCAx_AHCLKX ACLKX MCAx_ACLKX AFSX MCAx_AFSX AHCLKR ACLKR AFSR AXR0 AXR1 AXR2 AXR3 AXR[9:4] AMUTE AMUTEIN McASPx Pads MCAx_AHCLKR MCAx_ACLKR MCAx_AFSR MCAx_AXR0 MCAx_AXR1 MCAx_AXR2 MCAx_AXR3 The general connectivity attributes for the McASP modules are summarized in Table 22-1 Table 22-1. McASP Connectivity Attributes Attributes Type Power Domain Peripheral Domain Clock Domain PD_PER_L3S_GCLK (OCP Clock) PD_PER_MCASP_FCLK (Aux Clock) Reset Signals PER_DOM_RST_N Idle/Wakeup Signals Smart Idle Interrupt Requests 1 Transmit Interrupt per instance x_intr_pend - to MPU Subsystem (MCATXINTx) and PRU- ICSS (mcasp_x_intr_pend) 1 Receive Interrupt r_intr_pend - to MPU Subsystem (MCARXINTx) and PRU- ICSS (mcasp_r_intr_pend) DMA Requests 2 DMA requests per instance to EDMA (Transmit: AXEVTx, Receive: AREVTx) Physical Address L3 Slow slave port (data) L4 Peripheral slave port (CFG) 3928 Multichannel Audio Serial Port (McASP) SPRUH73E–October 2011–Revised May 2012 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
www.ti.com Integration 22.2.2 McASP Clock and Reset Management The McASP module uses functional clocks either generated internally (master mode) or supplied from its serial interface (slave mode). The internal interconnect interface clock is used for the module internal OCP interface. Internal registers select the source of the functional clocks and the applied divider ratio. Table 22-2. McASP Clock Signals Clock Signal Max Freq Reference / Source Comments ocp_clk 100 MHz CORE_COLKOUTM4 / 2 pd_per_l3s_gclk Interface clock From PRCM auxclk 26 MHz CLK_M_OSC pd_per_mcasp_gfclk Functional clock From PRCM 22.2.3 McASP Pin List The McASP external interface signals are shown in Table 22-3. Table 22-3. McASP Pin List Pin Type Description McASPx_AXR[3:0] I/O Audio transmit/receive pin McASPx_ACLKX I/O Transmit clock McASPx_FSX I/O Frame synch for transmit McASPx_AHCLKX I/O High speed transmit clock McASPx_ACLKR I/O Receive clock McASPx_FSR I/O Frame synch for receive McASPx_AHCLKR I/O High speed receive clock SPRUH73E–October 2011–Revised May 2012 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated 3929
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