Chapter 22 Multichannel Audio Serial Port (McASP).pdf
Chapter 22 Multichannel Audio Serial Port (McASP).pdf
Chapter 22 Multichannel Audio Serial Port (McASP).pdf
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Functional Description www.ti.com<br />
<strong>22</strong>.3.5.2 Receive Clock<br />
The receiver also has the option to operate synchronously from the ACLKX and AFSX signals. This is<br />
achieved when the ASYNC bit in the transmit clock control register (ACLKXCTL) is cleared to 0 (see<br />
Figure <strong>22</strong>-18). The receiver may be configured with different polarity (CLKRP) and frame sync data delay<br />
options from those options of the transmitter.<br />
The receive clock configuration is controlled by the following registers:<br />
• ACLKRCTL.<br />
• AHCLKRCTL.<br />
ACLKR<br />
pin<br />
Figure <strong>22</strong>-18. Receive Clock Generator Block Diagram<br />
AHCLKR_OUT<br />
AHCLKR_IN<br />
HCLKRM<br />
(internal/external)<br />
(AHCLKRCTL.15)<br />
Pin Muxing<br />
CLKRm<br />
(internal/external)<br />
(ACLKRCTL.5)<br />
CLKRP<br />
(polarity)<br />
(ACLKRCTL.7)<br />
1<br />
0<br />
1<br />
0<br />
0<br />
1<br />
1<br />
0<br />
Divider<br />
/1.../4096<br />
HCLKRDIV<br />
(AHCLKRCTL[11-0])<br />
Divider<br />
/1.../32<br />
CLKRDIV<br />
(ACLKRCTL[4-0])<br />
HCLKRP<br />
(Polarity)<br />
(AHCLKRCTL.14)<br />
1<br />
0<br />
XCLK<br />
(from Figure 16)<br />
RCLK<br />
ASYNC<br />
(ACLKXCTL.6)<br />
AUXCLK<br />
3942 <strong>Multichannel</strong> <strong>Audio</strong> <strong>Serial</strong> <strong>Port</strong> (<strong>McASP</strong>) SPRUH73E–October 2011–Revised May 2012<br />
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