Chapter 22 Multichannel Audio Serial Port (McASP).pdf

Functional Description www.ti.com
Finally, there is an important advantage to having separate control of pin direction (by PDIR), and the
choice of internal versus external clocking (by CLKRM/CLKXM). Depending on the specific device and
usage, you might select an external clock (CLKRM = 0), while enabling the internal clock divider, and the
clock pin as an output in the PDIR register (PDIR[ACLKR] = 1). In this case, the bit clock is an output
(PDIR[ACLKR] = 1) and, therefore, routed to the ACLKR pin. However, because CLKRM = 0, the bit clock
is then routed back to the McASP module as an "external" clock source. This may result in less skew
between the clock inside the McASP and the clock in the external device, thus producing more balanced
setup and hold times for a particular system. As a result, this may allow a higher serial clock rate interface.
22.3.10 Operation
This section discusses the operation of the McASP.
22.3.10.1 Data Transmission and Reception
The processor services the McASP by writing data to the XBUF register(s) for transmit operations, and by
reading data from the RBUF register(s) for receive operations. The McASP sets status flag and notifies
the processor whenever data is ready to be serviced. Section 22.3.10.1.1 discusses data ready status in
detail.
The XBUF and RBUF registers can be accessed through one of the two peripheral ports of the device:
• The data port (DAT): This port is dedicated for data transfers on the device.
• The configuration bus (CFG): This port is used for both data transfers and peripheral configuration
control on the device.
Section 22.3.10.1.2 and Section 22.3.10.1.3 discuss how to perform transfers through the data port and
the configuration bus.
Either the CPU or the DMA can be used to service the McASP through any of these two peripheral ports.
The CPU and DMA usages are discussed in Section 22.3.10.1.4 and Section 22.3.14.2.
22.3.10.1.1 Data Ready Status and Event/Interrupt Generation
22.3.10.1.1.1 Transmit Data Ready
The transmit data ready flag XDATA bit in the XSTAT register reflects the status of the XBUF register. The
XDATA flag is set when data is transferred from the XRBUF[n] buffers to the XRSR[n] shift registers,
indicating that the XBUF is empty and ready to accept new data from the processor. This flag is cleared
when the XDATA bit is written with a 1, or when all the serializers configured as transmitters are written by
the processor.
Whenever XDATA is set, an DMA event AXEVT is automatically generated to notify the DMA of the XBUF
empty status. An interrupt AXINT is also generated if XDATA interrupt is enabled in the XINTCTL register
(See Section 22.3.13.2 for details).
For DMA requests, the McASP does not require XSTAT to be read between DMA events. This means that
even if XSTAT already has the XDATA flag set to 1 from a previous request, the next transfer triggers
another DMA request.
Since all serializers act in lockstep, only one DMA event is generated to indicate that all active transmit
serializers are ready to be written to with new data.
Figure 22-26 shows the timing details of when AXEVT is generated at the McASP boundary. In this
example, as soon as the last bit (bit A0) of Word A is transmitted, the McASP sets the XDATA flag and
generates an AXEVT event. However, it takes up to 5 McASP system clocks (AXEVT Latency) before
AXEVT is active at the McASP boundary. Upon AXEVT, the processor can begin servicing the McASP by
writing Word C into the XBUF (Processor Service Time). The processor must write Word C into the XBUF
no later than the setup time required by the McASP (Setup Time).
The maximum Processor Service Time (Figure 22-26) can be calculated as:
Processor Service Time = Time Slot - AXEVT Latency - Setup Time
3956 Multichannel Audio Serial Port (McASP) SPRUH73E–October 2011–Revised May 2012
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