Chapter 22 Multichannel Audio Serial Port (McASP).pdf

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Functional Description www.ti.com 22.3.10.4.6 Clock Failure Detection 22.3.10.4.6.1 Clock-Failure Check Startup It is expected, initially, that the clock-failure circuits will generate an error until at least one measurement has been taken. Therefore, the clock failure interrupts, clock switch, and mute functions should not immediately be enabled, but be enabled only after a specific startup procedure. The startup procedure is: 1. For the transmit clock failure check: (a) Configure transmit clock failure detect logic (XMIN, XMAX, XPS) in the transmit clock check control register (XCLKCHK). (b) Clear transmit clock failure flag (XCKFAIL) in the transmit status register (XSTAT). (c) Wait until first measurement is taken (> 32 AHCLKX clock periods). (d) Verify no clock failure is detected. (e) Repeat steps b–d until clock is running and is no longer issuing clock failure errors. (f) After the transmit clock is measured and falls within the acceptable range, the following may be enabled: (i) transmit clock failure interrupt enable bit (XCKFAIL) in the transmitter interrupt control register (XINTCTL). (ii) transmit clock failure detect autoswitch enable bit (XCKFAILSW) in the transmit clock check control register (XCLKCHK). (iii) mute option (XCKFAIL) in the mute control register (AMUTE). 2. For the receive clock failure check: (a) Configure receive clock failure detect logic (RMIN, RMAX, RPS) in the receive clock check control register (RCLKCHK). (b) Clear receive clock failure flag (RCKFAIL) in the receive status register (RSTAT). (c) Wait until first measurement is taken (> 32 AHCLKR clock periods). (d) Verify no clock failure is detected. (e) Repeat steps b–d until clock is running and is no longer issuing clock failure errors. (f) After the receive clock is measured and falls within the acceptable range, the following may be enabled: (i) receive clock failure interrupt enable bit (RCKFAIL) in the receiver interrupt control register (RINTCTL). (ii) mute option (RCKFAIL) in the mute control register (AMUTE). 3968 Multichannel Audio Serial Port (McASP) SPRUH73E–October 2011–Revised May 2012 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
www.ti.com Functional Description 22.3.10.4.6.2 Transmit Clock Failure Check and Recovery The transmit clock failure check circuit (Figure 22-31) works off both the internal McASP system clock and the external high-frequency serial clock (AHCLKX). It continually counts the number of system clocks for every 32 high rate serial clock (AHCLKX) periods, and stores the count in XCNT of the transmit clock check control register (XCLKCHK) every 32 high rate serial clock cycles. The logic compares the count against a user-defined minimum allowable boundary (XMIN), and automatically flags an interrupt (XCKFAIL in XSTST) when an out-of-range condition occurs. An out-ofrange minimum condition occurs when the count is smaller than XMIN. The logic continually compares the current count (from the running system clock counter) against the maximum allowable boundary (XMAX). This is in case the external clock completely stops, so that the counter value is not copied to XCNT. An out-of-range maximum condition occurs when the count is greater than XMAX. Note that the XMIN and XMAX fields are 8-bit unsigned values, and the comparison is performed using unsigned arithmetic. An out-of-range count may indicate either that an unstable clock was detected, or that the audio source has changed and a new sample rate is being used. In order for the transmit clock failure check circuit to operate correctly, the high-frequency serial clock divider must be taken out of reset regardless if AHCLKX is internally generated or externally sourced. External AHCLKX pin input McASP clock (A) system Figure 22-31. Transmit Clock Failure Detection Circuit Block Diagram Count to 32 Prescale /1 to /256 4 XCLKCHK[3−0] XPS XCLKCHK[15−8] 8 XMIN XCLKCHK[23−16] XMAX 8 Sync to system clock Clear 8−bit counter Count 8 Load XCLKCHK[31−24] XCNT 8 XCNTXMAX? 8 True True OR XCLKCHK.7 XCKFAILSW Set XSTAT.2 Interrupt XCKFAIL mute A Refer to device data manual for the McASP system clock source. This is not the same as AUXCLK. AND Switch to internal AHCLKX1 reset McASP transmitter, enter underrun (D15 mode only) send BMC 0’s when clock is bad external SPRUH73E–October 2011–Revised May 2012 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated 3969
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