Chapter 22 Multichannel Audio Serial Port (McASP).pdf

Functional Description www.ti.com
The third basic element of a synchronous serial interface is the frame synchronization signal, also referred
to as frame sync in this document.
Frame A frame contains one or multiple slots, as determined by the desired protocol. Figure 22-16 shows an example frame
of data and the frame definitions. Figure 22-16 does not specify whether the frame sync (FS) is for transmit (AFSX)
or receive (AFSR) because the definitions of terms apply to both receive and transmit interfaces. In operation, the
transmitter uses AFSX and the receiver uses AFSR. Optionally, the receiver can use AFSX as the frame sync when
the transmitter and receiver of the McASP are configured to operate synchronously.
This section only shows the generic definition of the frame sync. See Section 22.3.3 and Section 22.3.8.1
for details on the frame sync formats required for the different transfer modes and protocols (burst mode,
TDM mode and I2S format, DIT mode and S/PDIF format).
Figure 22-16. Definition of Frame and Frame Sync Width
FS
AXRn
Slot 0 Slot 1
Slot
Frame
Frame sync width
(1) In this example, there are two slots in a frame, and FS duration of slot length is shown.
Other terms used throughout the document:
TDM Time-division multiplexed. See Section 22.3.3.1 for details on the TDM protocol.
DIR Digital audio interface receive. The McASP does not natively support receiving in the S/PDIF format. The
McASP supports I2S format output by an external DIR device.
DIT Digital audio interface transmit. The McASP supports transmitting in S/PDIF format on up to all data pins
configured as outputs.
I2S Inter-Integrated Sound protocol, commonly used on audio interfaces. The McASP supports the I2S protocol as
part of the TDM mode (when configured as a 2-slot frame).
Slot or For TDM format, the term time slot is interchangeable with the term slot defined in this section. For DIT format, a
Time Slot McASP time slot corresponds to a DIT subframe.
22.3.5 Clock and Frame Sync Generators
The McASP clock generators are able to produce two independent clock zones: transmit and receive
clock zones. The serial clock generators may be programmed independently for the transmit section and
the receive section, and may be completely asynchronous to each other. The serial clock (clock at the bit
rate) may be sourced:
• Internally - by passing through two clock dividers off the internal clock source (AUXCLK).
• Externally - directly from ACLKR/X pin.
• Mixed - an external high-frequency clock is input to the McASP on either the AHCLKX or AHCLKR
pins, and divided down to produce the bit rate clock.
In the internal/mixed cases, the bit rate clock is generated internally and should be driven out on the
ACLKX (for transmit) or ACLKR (for receive) pins. In the internal case, an internally-generated highfrequency
clock may be driven out onto the AHCLKX or AHCLKR pins to serve as a reference clock for
other components in the system.
The McASP requires a minimum of a bit clock and a frame sync to operate, and provides the capability to
reference these clocks from an external high-frequency master clock. In DIT mode, it is possible to use
only internally-generated clocks and frame syncs. Both the AUXCLK and System Clock are generated
from SYSCLK2 (CLKDIV6 domain).
3940 Multichannel Audio Serial Port (McASP) SPRUH73E–October 2011–Revised May 2012
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