Vivado Design Suite Tutorial - Xilinx

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2. Select the existing timing.xdc file as shown below, and click OK. Figure 13: No Target Constraints File Step 5: Saving Constraints Note: After you save the constraints, the Save Constraints icon becomes disabled, indicating the constraint files are up-to-date. 3. Double-click on the timing.xdc file in the lab1 constraint set, in the Sources window. The timing.xdc opens in the Vivado text editor, and shows the create_clock command with context-sensitive text coloring. Figure 14: timing.xdc file Tip: The Vivado IDE can be customized to support any of a number of third party text editors. Refer to the Vivado Design Suite User Guide: Using the Integrated Design Environment (UG893) for more information. Using Constraints www.xilinx.com 14 UG945 (v2012.2) August 8, 2012
Step 6: Using the Timing Constraint Spreadsheet Step 6: Using the Timing Constraint Spreadsheet You can create other timing constraints following the process described in Step 3: Creating Clock Constraints. You can also enter constraints directly into the spreadsheet of the Timing Constraints window, as shown in Figure 11: The Added sysClk Constraint. By default, the Vivado IDE does not time paths to or from I/O ports in the design. You must first assign input/output delay constraints to the ports. In this step you assign an input delay onto the or1200_clmode port. Before that though, generate a custom timing report for paths starting from this port. 1. Select Tools > Timing > Report Timing to bring up the Report Timing dialog box. Figure 15: Report Timing command The report Timing dialog box opens as shown in Figure 16. To report timing from the specific input port, set the From field as follows: get_ports {or1200_clmode} You can type the get_ports command directly into the Start Points From field, or use the browse button ( ), and search for the specific port in the Choose Start Points dialog box. Figure 16: Report Timing dialog box Using Constraints www.xilinx.com 15 UG945 (v2012.2) August 8, 2012
Page 1 and 2: Vivado Design Suite Tutorial Using
Page 3 and 4: Table of Contents Vivado Using Cons
Page 5 and 6: Software Requirements Software Requ
Page 7 and 8: The project saves to the specified
Page 9 and 10: Step 3: Using a Timing Constraint W
Page 11 and 12: Figure 10: Specify Clock Sources c.
Page 13: Step 4: Reporting Clock Interaction
Page 17 and 18: Step 6: Using the Timing Constraint
Page 19 and 20: Lab #2: Setting Physical Constraint
Page 21 and 22: Step 2: Adding Placement Constraint
Page 23 and 24: Step 4: Defining Constraints with C
Page 25 and 26: Step 5: Saving Constraints Because

Vivado Design Suite Tutorial - Xilinx

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