Vivado Design Suite Tutorial - Xilinx

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Figure 28: Find dialog box Step 4: Defining Constraints with Cell Properties 1. Select Edit > Find to open the Find dialog box, as shown in Figure 28, and search for Block RAMs. a. Specify Find Instances. b. Under Criteria, specify Type is Block Ram c. Click OK The Find Results window displays. 2. Select the first reported cell, which should be the RAMB36E1 cell: fftEngine/fftInst/ingressLoop[7].ingressFifo/… In the Attributes tab of the Instance Properties window, you can see the DOA_REG and DOB_REG are set to zero, indicating that the output registers are disabled. 3. Generate a custom timing report from this cell, either from Tools > Timing > Report Timing or directly from the Tcl Console. The Tcl command is: report_timing -from [get_cells fftEngine/fftInst/ingressLoop[7].ingressFifo/buffer_fifo/infer_fifo.block_ ram_performance.fifo_ram_reg] Tip: You can copy and paste the cell name from the General tab of the Instance Properties window into the Tcl console. In the data path section of the report, 1.800ns is added for this RAM. 4. In the Attributes tab of the Instance Properties window, select the DOA_REG and DOB_REG properties for this cell, and change their values from “0” to “1”. 5. Click the Apply button in the Instance Properties window. You can see the two set_property commands run in the Tcl Console. Using Constraints www.xilinx.com 24 UG945 (v2012.2) August 8, 2012
Step 5: Saving Constraints Because these are properties on objects, and not directly defined as timing constraints, you must update the timing data in the Vivado tools, and rerun the timing report, to see these property changes have an effect. 6. Update the timing by typing the following in the Tcl Console: update_timing -full 7. Rerun the timing report from the selected cell. The Tcl command will be: report_timing -from [get_selected_objects] Notice that the data path delay for the RAM is now 0.622ns. Next, set the configuration mode on the design. This is another property that is a physical constraint, in this case of the design rather than of a cell. To begin, list all of the properties on the current design. 1. List the properties of the design in the Tcl Console: list_property [current_design] This command returns the list of all properties in the current design. To make the list more readable, you can use the standard Tcl join command to combine the properties output with “\n” newline character, resulting in each property displaying on a separate line. join [list_property [current_design]] \n 2. The specific property of interest is CONFIG_MODE. To see what values this particular property can accept, use the list_property_value Tcl command: join [list_property_value CONFIG_MODE [current_design]] \n 3. Set the CONFIG_MODE property to M_SERIAL for this project: set_property CONFIG_MODE M_SERIAL [current_design] The configuration mode has now been set. 4. Use the get_property command to check that the CONFIG_MODE property was correctly set: get_property CONFIG_MODE [current_design] The property value M_SERIAL is returned by the Vivado tool. Step 5: Saving Constraints Notice that the Save Constraints icon is enabled because there are new design constraints. The cell and design properties you modified in Lab #2 have been added to the Vivado tool in-memory design, but are not yet saved to the target constraint file. 1. Click the Save Constraints button. The physical constraints you defined over the course of this tutorial are saved to the target constraint file. Using Constraints www.xilinx.com 25 UG945 (v2012.2) August 8, 2012
Page 1 and 2: Vivado Design Suite Tutorial Using
Page 3 and 4: Table of Contents Vivado Using Cons
Page 5 and 6: Software Requirements Software Requ
Page 7 and 8: The project saves to the specified
Page 9 and 10: Step 3: Using a Timing Constraint W
Page 11 and 12: Figure 10: Specify Clock Sources c.
Page 13 and 14: Step 4: Reporting Clock Interaction
Page 15 and 16: Step 6: Using the Timing Constraint
Page 17 and 18: Step 6: Using the Timing Constraint
Page 19 and 20: Lab #2: Setting Physical Constraint
Page 21 and 22: Step 2: Adding Placement Constraint
Page 23: Step 4: Defining Constraints with C

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