Xilinx Command Line Tools User Guide: (UG628)

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Chapter 1: Introduction Specification Examples Architecture only virtex4 virtex5 spartan3 spartan3a xc9500 xpla3 (CoolRunner XPLA3 devices) Device only xc4vfx12 xc3s100e DevicePackage xc4fx12sf363 xc3s100evq100 Device-Package xc4vfx12-sf363 xc3s100e-vq100 DeviceSpeed-Package xc4vfx1210-sf363 xc3s100e4-vq100 DevicePackage-Speed xc4fx12sf363-10 xc3s100evq100-4 Device-Speed-Package xc4vfx12-10-sf363 xc3s100e-4-vq100 Device-SpeedPackage xc4vfx12-10sf363 xc3s100e-4vq100 Invoking Command Line Programs You start Xilinx® command line programs by entering a command at the Linux or DOS command line. See the program-specific chapters in this book for the appropriate syntax Xilinx also offers the XFLOW program, which lets you automate the running of several programs at one time. See the XFLOW chapter for more information. Command Line Tools User Guide 14 www.xilinx.com UG628 (v 14.2) July 25, 2012
Design Flow Design Flow Overview Chapter 2 This chapter describes the process for creating, implementing, verifying, and downloading designs for Xilinx® FPGA and CPLD devices. For a complete description of Xilinx FPGA and CPLDs devices, refer to the Xilinx Data Sheets at: http://www.xilinx.com/support/ The standard design flow comprises the following steps: 1. Design Entry and Synthesis - Create your design using a Xilinx®-supported schematic editor, a Hardware Description Language (HDL) for text-based entry, or both. If you use an HDL for text-based entry, you must synthesize the HDL file into an EDIF file or, if you are using the Xilinx Synthesis Technology (XST) GUI, you must synthesize the HDL file into an NGC file. 2. Design Implementation - Convert the logical design file format, such as EDIF, that you created in the design entry and synthesis stage into a physical file format by implementing to a specific Xilinx architecture. The physical information is contained in the Native Circuit Description (NCD) file for FPGAs and the VM6 file for CPLDs. Then create a bitstream file from these files and optionally program a PROM or EPROM for subsequent programming of your Xilinx device. 3. Design Verification - Using a gate-level simulator or cable, ensure that your design meets timing requirements and functions properly. See the iMPACT online help for information about Xilinx download cables and demonstration boards. The full design flow is an iterative process of entering, implementing, and verifying your design until it is correct and complete. The command line tools provided with the ISE® Design Suite allow quick design iterations through the design flow cycle. Xilinx devices permit unlimited reprogramming. You do not need to discard devices when debugging your design in circuit. Command Line Tools User Guide UG628 (v 14.2) July 25, 2012 www.xilinx.com 15
Page 1 and 2: Command Line Tools User Guide (Form
Page 3 and 4: Date Version 1/18/2012 13.4 downloa
Page 5 and 6: MAP Process........................
Page 7 and 8: Chapter 18 IBISWriter .............
Page 9 and 10: Introduction Chapter 1 This chapter
Page 11 and 12: -h (Help) Syntax You can use the fi
Page 13: -p (Part Number) Syntax This option
Page 17 and 18: Xilinx Software Design Flow (FPGAs)
Page 19 and 20: Partitions PXML File Chapter 2: De
Page 21 and 22: Chapter 2: Design Flow Macros are n
Page 23 and 24: Design Implementation Flow (FPGAs)
Page 25 and 26: Chapter 2: Design Flow Note MAP pro
Page 27 and 28: Simulation Chapter 2: Design Flow T
Page 29 and 30: Chapter 2: Design Flow Note It is u
Page 31 and 32: Static Timing Analysis (FPGAs Only)
Page 33 and 34: PARTGen PARTGen Overview Device Sup
Page 35 and 36: Chapter 3: PARTGen For IOSTD_DRIVE
Page 37 and 38: Chapter 3: PARTGen NUM_BLK_RAMS=# B
Page 39 and 40: PARTGen Syntax Chapter 3: PARTGen C
Page 41 and 42: -intstyle (Integration Style) Synta
Page 43 and 44: NetGen NetGen Overview NetGen Flows
Page 45 and 46: NetGen Simulation Flow Chapter 4: N
Page 47 and 48: CPLD Timing Simulation Chapter 4: N
Page 49 and 50: Syntax -bx bram_output_dir -dir (Di
Page 51 and 52: Chapter 4: NetGen Settings made wit
Page 53 and 54: Syntax -ne Chapter 4: NetGen By def
Page 55 and 56: -rpw (Specify the Pulse Width for R
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Page 61 and 62: Options for NetGen Static Timing An
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Chapter 4: NetGen The base name of
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Logical Design Rule Check (DRC) Log
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Clock Buffer Check Name Check Primi
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NGDBuild NGDBuild Overview This cha
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Chapter 6: NGDBuild the output Nati
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-a (Add PADs to Top-Level Port Sign
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-intstyle (Integration Style) Synta
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-sd /home/macros/counter -sd /home/
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MAP MAP Overview MAP Design Flow MA
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MAP Output Files MAP Process Output
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Chapter 7: MAP pcf_file is the name
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Syntax -activityfile activityfile .
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-equivalent_register_removal (Remov
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off (the default) will disable the
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Chapter 7: MAP The architecture you
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Chapter 7: MAP The results from the
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Syntax -xe effort_level Chapter 7:
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MAP Report (MRP) File Chapter 7: MA
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Chapter 7: MAP • Area Group & Par
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Section 1 - Errors ----------------
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-----------------------------------
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Halting MAP Chapter 7: MAP To halt
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Physical Design Rule Check DRC Over
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-z (Report Incomplete Programming)
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Place and Route (PAR) PAR Overview
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PAR Output Files PAR Process Placin
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Chapter 9: Place and Route (PAR) pc
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By default, the filter file name is
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Chapter 9: Place and Route (PAR) Th
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Syntax -w Chapter 9: Place and Rout
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PAR Report Layout The PAR report is
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Number of GTXE2_CHANNELs: 0 out of
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Chapter 9: Place and Route (PAR) TS
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Sample Guide Report File Chapter 9:
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Halting PAR Chapter 9: Place and Ro
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SmartXplorer Overview Key Benefits
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Using Synplify Chapter 10: SmartXpl
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On Linux - Chapter 10: SmartXplorer
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The Run Summary table contains seve
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Custom Strategies Chapter 10: Smart
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Running Strategies in Parallel Chap
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Example Chapter 10: SmartXplorer If
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Reports smartxplorer.html There are
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smartxplorer.txt DesignFile_sx.log
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Files and Directories SmartXplorer
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Syntax -area_report [on|off|column_
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Chapter 10: SmartXplorer Note This
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Chapter 10: SmartXplorer The names
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Chapter 10: SmartXplorer When you s
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-ucf ucf_file Chapter 10: SmartXplo
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XPWR XPWR Overview This chapter is
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XPWR Command Line Options The follo
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-vid (Voltage ID Used) Syntax Chapt
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Power Reports Chapter 11: XPWR An a
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PIN2UCF PIN2UCF Overview This chapt
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Chapter 12: PIN2UCF User-specified
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Chapter 12: PIN2UCF pin2ucf ncd_fil
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TRACE TRACE Overview Chapter 13 Thi
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TRACE Options This section describe
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Syntax -l limit Chapter 13: TRACE N
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-u (Report Uncovered Paths) Syntax
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Chapter 13: TRACE To correct timing
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Chapter 13: TRACE When the source a
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Data Sheet Report Chapter 13: TRACE
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Pad to Pad ------------------------
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Chapter 13: TRACE Summary Report (W
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Error Report ad11 | 0.263(R) | 0.55
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Verbose Report Data Sheet report: -
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Chapter 13: TRACE (fanout=1) RAM16.
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OFFSET IN Constraint Examples Chapt
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OFFSET IN Detailed Path Data Chapte
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Requirement: 4.000ns Data Path Dela
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Chapter 13: TRACE Note The clock fa
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PERIOD Header PERIOD Path Chapter 1
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Chapter 13: TRACE At the end of the
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Speedprint Speedprint Overview Spee
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Speedprint Example Report Two: spee
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Speedprint Command Line Syntax The
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BitGen BitGen Overview Design Flow
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File Type Format File Contents Note
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Syntax -bd file_name {.elf|.mem} Ch
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-g (Set Configuration) • ActiveRe
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pi_sync_mode BusyPin CclkPin Compre
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CrcCoverage CsPin Chapter 15: BitGe
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DonePin DonePipe Chapter 15: BitGen
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ExtMasterCclk_divide Determines if
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HswapenPin icap_select IEEE1532 Ini
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M0Pin M1Pin M2Pin Chapter 15: BitGe
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next_config_reboot Chapter 15: BitG
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PowerdownPin ProgPin RdWrPin ReadBa
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SPI_buswidth Chapter 15: BitGen Set
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TdoPin Chapter 15: BitGen Adds a pu
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-j (No BIT File) Syntax When using
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BSDLAnno BSDLAnno Overview This cha
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Syntax -intstyle ise|xflow|silent W
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BSDLAnno Package Pin-Mapping Exampl
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Chapter 16: BSDLAnno About Boundary
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BSDLAnno Header Comments Chapter 16
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PROMGen PROMGen Overview This chapt
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PROMGen Options Chapter 17: PROMGen
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Here is the multiple file syntax: p
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-o (Output File Name) Syntax -p (PR
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-x (Specify Xilinx PROM) Syntax Cha
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IBISWriter IBISWriter Overview IBIS
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IBISWriter Options This section pro
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CPLDFit CPLDFit Overview This chapt
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CPLDFit Options CPLDFit uses the fo
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Chapter 19: CPLDFit The maximum lim
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-nomlopt (Disable Multi-level Logic
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Syntax -terminate [pullup|keeper|fl
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TSIM TSIM Overview This chapter des
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TAEngine TAEngine Overview Chapter
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Hprep6 Hprep6 Overview Hprep6 Desig
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-n (Specify Signature Value for Rea
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XFLOW XFLOW Overview XFLOW Design F
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XFLOW Output Files Chapter 23: XFLO
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XFLOW Syntax Chapter 23: XFLOW File
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Syntax -fit (Fit a CPLD) Syntax -ec
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-sta (Create a File for Static Timi
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Flow Files Option Files for -tsim F
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Chapter 23: XFLOW This line lists t
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XFLOW Options Chapter 23: XFLOW Thi
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Chapter 23: XFLOW In this example,
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Running XFLOW Chapter 23: XFLOW You
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NGCBuild NGCBuild Overview This cha
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NGCBuild Options Chapter 24: NGCBui
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Syntax -filter [filter_file ] By de
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-verbose (Report All Messages) Synt
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Compxlib Compxlib Overview Design F
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Compxlib Options This section descr
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-dir (Output Directory) Syntax Chap
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Syntax -log log_file -p (Simulator
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Chapter 25: Compxlib When mapping t
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FAST_COMPILE If the value is off, C
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OPTION:mti_se:vhdl:i:-source -93 -n
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OPTION:ncsim:verilog:c:-MESSAGES -N
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XWebTalk WebTalk Overview Chapter 2
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Syntax -install on|off on turns Web
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Tcl Reference Tcl Overview Tcl Devi
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Xilinx Namespace Chapter 27: Tcl Re
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Process Properties - Synthesize Pro
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Property Name Type Allowed Values i
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Process Properties - Translate Proc
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Xilinx Tcl Commands for General Use
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lib_vhdl is the Tcl command name. g
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Example 1 % process get "Map" statu
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Chapter 27: Tcl Reference property_
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project is the Tcl command name. cl
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project open (open an ISE project)
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Example 3 % project set "Map Effort
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Example % xfile get stopwatch.vhd t
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Example 2 % xfile set stopwatch.vhd
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Syntax % globals get property_name
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Available subcommands are: • appe
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collection is the Tcl command name.
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Syntax % collection index collectio
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collection set (set the property fo
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Chapter 27: Tcl Reference This exam
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The following information can be re
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For More Information Example Tcl Sc
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Chapter 27: Tcl Reference The follo
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Chapter 27: Tcl Reference The first
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ISE Design Suite Files Appendix A T
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Name Type Produced By Description A
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Name Type Produced By Description A
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EDIF2NGD and NGDBuild EDIF2NGD Over
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EDIF2NGD Input Files EDIF2NGD uses
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Appendix B: EDIF2NGD and NGDBuild Y
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Bus Matching Appendix B: EDIF2NGD a
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Netlist Launcher Rules Files Append
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Value Types in Key Statements Appen
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Example 4: User Rule // URF Example
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Additional Resources • Xilinx Glo
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Xilinx Command Line Tools User Guide: (UG628)

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