Xilinx Command Line Tools User Guide: (UG628)

Chapter 2: Design Flow
Mapping (FPGAs Only)
Design Implementation Flow (CPLDs)
For FPGAs, the MAP command line program maps a logical design to a Xilinx® FPGA.
The input to MAP is an NGD file, which contains a logical description of the design in
terms of both the hierarchical components used to develop the design and the lower-level
Xilinx primitives, and any number of NMC (hard placed-and-routed macro) files, each
of which contains the definition of a physical macro. MAP then maps the logic to the
components (logic cells, I/O cells, and other components) in the target Xilinx FPGA.
The output design from MAP is an NCD file, which is a physical representation of
the design mapped to the components in the Xilinx FPGA. The NCD file can then be
placed and routed, using the PAR command line program. See the MAP chapter for
detailed information.
Command Line Tools User Guide
24 www.xilinx.com UG628 (v 14.2) July 25, 2012