Xilinx Command Line Tools User Guide: (UG628)

Chapter 4: NetGen
options is one or more of the options listed in the Options for NetGen Simulation
Flow section. In addition to common options, this section also contains Verilog and
VHDL-specific options.
input_file is the input file name. If an NGD file is used, the .ngd extension must be
specified.
NetGen Timing Simulation Flow
This section describes the NetGen Timing Simulation flow, which is used for timing
verification on FPGA and CPLD designs. For FPGA designs, timing simulation is done
after PAR, but may also be done after MAP if only component delay and no route
delay information is needed. When performing timing simulation, you must specify
the type of netlist you want to create: Verilog or VHDL. In addition to the specified
netlist, NetGen also creates an SDF file as output. The output Verilog and VHDL netlists
contain the functionality of the design and the SDF file contains the timing information
for the design.
Input file types depend on whether you are using an FPGA or CPLD design. Please refer
to FPGA Timing Simulation and CPLD Timing Simulation below for design-specific
information, including input file types.
FPGA Timing Simulation
You can verify the timing of an FPGA design using the NetGen Timing Simulation flow
to generate a Verilog or VHDL netlist and an SDF file. The figure below illustrates the
NetGen Timing Simulation flow using an FPGA design.
The FPGA Timing Simulation flow uses the following files as input:
• NCD - This physical design file may be mapped only, partially or fully placed, or
partially or fully routed.
• PCF (optional) - This is a physical constraints file. If prorated voltage or temperature
is applied to the design, the PCF must be included to pass this information to
NetGen. See -pcf (PCF File) for more information.
• ELF (MEM) (optional) - This file populates the Block RAMs specified in the .bmm
file. See -bd (Block RAM Data File) for more information.
The FPGA Timing Simulation flow creates the following output files:
• SDF file - This SDF 3.0 compliant standard delay format file contains delays
obtained from the input design files.
• V file - This is a IEEE 1364-2001 compliant Verilog HDL file that contains the netlist
information obtained from the input design files. This file is a simulation model. It
cannot be synthesized, and can only be used for simulation.
• VHD file - This VHDL IEEE 1076.4 VITAL-2000 compliant VHDL file contains the
netlist information obtained from the input design files. This file is a simulation
model. It cannot be synthesized, and can only be used for simulation.
Command Line Tools User Guide
46 www.xilinx.com UG628 (v 14.2) July 25, 2012