Xilinx Command Line Tools User Guide: (UG628)

Table of Contents
Revision History ....................................................................................................2
Chapter 1 Introduction.................................................................................................9
Command Line Program Overview ......................................................................9
Command Line Syntax......................................................................................... 10
Command Line Options ...................................................................................... 10
Invoking Command Line Programs.................................................................... 14
Chapter 2 Design Flow...............................................................................................15
Design Flow Overview ........................................................................................ 15
Design Entry and Synthesis ................................................................................ 18
Design Implementation....................................................................................... 22
Design Verification............................................................................................... 25
FPGA Design Tips ............................................................................................... 31
Chapter 3 PARTGen ...................................................................................................33
PARTGen Overview............................................................................................. 33
PARTGen Syntax.................................................................................................. 39
PARTGen Command Line Options..................................................................... 39
Chapter 4 NetGen .......................................................................................................43
NetGen Overview ................................................................................................ 43
NetGen Simulation Flow..................................................................................... 45
NetGen Equivalence Checking Flow.................................................................. 55
NetGen Static Timing Analysis Flow ................................................................. 59
Preserving and Writing Hierarchy Files ............................................................. 63
Dedicated Global Signals in Back-Annotation Simulation .............................. 65
Chapter 5 Logical Design Rule Check (DRC)...........................................................67
Logical DRC Overview ........................................................................................ 67
Logical DRC Checks ............................................................................................ 67
Chapter 6 NGDBuild...................................................................................................71
NGDBuild Overview........................................................................................... 71
NGDBuild Syntax ................................................................................................ 74
NGDBuild Options.............................................................................................. 74
Chapter 7 MAP............................................................................................................81
MAP Overview..................................................................................................... 81
Command Line Tools User Guide
4 www.xilinx.com UG628 (v 14.2) July 25, 2012