Xilinx Command Line Tools User Guide: (UG628)

Chapter 2: Design Flow
You can enter constraints manually or use the Constraints Editor or FPGA Editor, which
are graphical user interface (GUI) tools provided by Xilinx®. You can use the Timing
Analyzer GUI or TRACE command line program to evaluate the circuit against these
constraints by generating a static timing analysis of your design. See the TRACE chapter
and the online Help provided with the ISE® Design Suite for more information. For
more information on constraints, see the Constraints Guide (UG625).
Mapping Constraints (FPGAs Only)
You can specify how a block of logic is mapped into CLBs using an FMAP for all
Spartan® and Virtex® FPGA architectures. These mapping symbols can be used in
your schematic. However, if you overuse these specifications, it may be difficult to
route your design.
Block Placement
Block placement can be constrained to a specific location, to one of multiple locations, or
to a location range. Locations can be specified in the schematic, with synthesis tools,
or in the User Constraints File (UCF). Poor block placement can adversely affect both
the placement and the routing of a design. Only I/O blocks require placement to meet
external pin requirements.
Timing Specifications
You can specify timing requirements for paths in your design. PAR uses these timing
specifications to achieve optimum performance when placing and routing your design.
Netlist Translation Programs
Design Implementation
Netlist translation programs let you read netlists into the Xilinx® software tools.
EDIF2NGD lets you read an Electronic Data Interchange Format (EDIF) 2 0 0 file. The
NGDBuild program automatically invokes these programs as needed to convert your
EDIF file to an NGD file, the required format for the Xilinx software tools. NGC files
output from the Xilinx XST synthesis tool are read in by NGDBuild directly.
You can find detailed descriptions of the EDIF2NGD, and NGDBuild programs in the
NGDBuild chapter and the EDIF2NGD and NGDBuild Appendix.
Design Implementation begins with the mapping or fitting of a logical design file to a
specific device and is complete when the physical design is successfully routed and a
bitstream is generated. You can alter constraints during implementation just as you did
during the Design Entry step. See Constraints for information.
The following figure shows the design implementation process for FPGA designs:
Command Line Tools User Guide
22 www.xilinx.com UG628 (v 14.2) July 25, 2012