Xilinx Command Line Tools User Guide: (UG628)

Chapter 2: Design Flow
NetGen
Back-Annotation Flow for FPGAs
Back-Annotation (CPLDs)
NetGen is a command line program that distributes information about delays, setup
and hold times, clock to out, and pulse widths found in the physical Native Circuit
Description (NCD) design file back to the logical Native Generic Database (NGD) file
and generates a Verilog or VHDL netlist for use with supported timing simulation,
equivalence checking, and static timing analysis tools.
NetGen reads an NCD as input. The NCD file can be a mapped-only design, or a
partially or fully placed and routed design. An NGM file, created by MAP, is an optional
source of input. NetGen merges mapping information from the optional NGM file with
placement, routing, and timing information from the NCD file.
Note NetGen reads an NGA file as input to generate a timing simulation netlist for
CPLD designs.
See the NetGen chapter for detailed information.
Functional Simulation
Functional simulation determines if the logic in your design is correct before you
implement it in a device. Functional simulation can take place at the earliest stages of
the design flow. Because timing information for the implemented design is not available
at this stage, the simulator tests the logic in the design using unit delays.
Command Line Tools User Guide
28 www.xilinx.com UG628 (v 14.2) July 25, 2012